外文翻译--三位半LCDLED显示AD转换器

《外文翻译--三位半LCDLED显示AD转换器》由会员分享，可在线阅读，更多相关《外文翻译--三位半LCDLED显示AD转换器（16页珍藏版）》请在毕设资料网上搜索。

1、第 1 页 共 16 页 中文 3390字 213Digit, LCD/LED Display, A/D Converters Abstract: The Intersil ICL7106 and ICL7107 are high performance, low power, 213digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crys

2、tal display (LCD) and includes a multiplexed backplane drive； the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less than 10V, zero drift

3、 of less than 1V/ , input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true

4、 economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. Keyword: 213Digit LCD/LED Display A/D Converters 1 Features (1)Guaranteed Zero Reading for 0V Input on All Scales (2)1pA Typical Inpu

5、t Current (3)True Differential Input and Reference, Direct Display Drive -LCD ICL7106, LED LCL7107 (4)Low Noise - Less Than 15VP-P (5)On Chip Clock and Reference (6)Low Power Dissipation - Typically Less Than 10mW (7)No Additional Active Circuits Required 2 Detailed Description 2.1 Analog Section Fi

6、gure 1 shows the Analog Section for the ICL7106 and ICL7107. Each measurement 第 2 页 共 16 页 cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). FIGURE 1 ANALOG SECTION OF ICL7106 AND ICL7107 2.2 Auto-Zero Phase During auto-zero three

7、 things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset vol

8、tages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10V. 2.3 Signal Integrate Phase During signal integrate, the auto-zero loop

9、is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either su

10、pply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, 第 3 页 共 16 页 the polarity of the integrated signal is determined. 2.4 De-Integrate Phase

11、The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the int

12、egrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: DISPLAY COUNT= REFINVV1000 2.5 Differential Input The input can accept differential voltages anywhere within the common mode range

13、of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive commo

14、n mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the

15、 recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. 2.6 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of co

16、mmon mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is