外文翻译--版图中常见的几个失效机制

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1、 通 信 工 程 学 院 毕 业 生 文 献 翻 译 版图中常见的几个失效机制 学 生 姓 名 ： XXX 专 业： 微电子 班 级： 微电 092 导师姓名 (职称 )： XXX（ 讲师 ） 文献提交日期： 2013 年 03 月 01 日 版图中常见的几个失效机制 （ ） Integrated circuits are incredibly complex devices, and few of them are perfect. Most contain subtle weaknesses and flaws, which predispose them toward eventual

2、failure. Such components can fail catastrophically and without warning after operating perfectly for many years. Engineers have traditionally relied on quality assurance programs to uncover hidden design flaws. Operation under stressful conditions can accelerate many failure mechanisms, but not ever

3、y design flaw can be found by testing. The designer must therefore find and eliminate as many of these flaws as possible. The layout of an integrated circuit contributes to many types of failures. If the designer knows about potential weaknesses, then safeguards can be built into the integrated circ

4、uit to protect it against failure mechanisms that can be partially or entirely. Electrostatic Discharge(ESD) Almost any form of friction can generate static electricity. For example, if you shuffle across a carpet in dry weather and then touch a metal doorknob, a visible spark will leap from finger

5、to doorknob. The human body acts as a capacitor, and the act of shuffling across a carpet charges this capacitance to a potential of 10000V or more. When a finger is brought near the doorknob, the sudden discharge creates a visible spark and a perceptible electrical shock. A discharge of less than 5

6、0V will destroy the gate dielectric of a typical integrated MOS transistor. Voltages this low produce neither visible sparks nor perceptible electrical shock. Almost any human or mechanical activity can produce such low-level electrostatic discharges. Proper handing precautions will minimize the ris

7、ks of electrostatic discharge. ESD-sensitive components (including integrated circuits) should always be stored in static-shielded packaging. Grounded wrist straps and soldering irons can reduce potential opportunities for ESD discharges Humidifiers, ionizers, and antistaticmats can minimize the bui

8、ldup of static charges around workstations and machinery. These precautions reduce but do not eliminate ESD damage, so manufacturers routinely include special ESD protection structures onboard integrated circuits.These structures are designed to absorb and dissipate moderate leaves of ESD energy wit

9、hout damage. Special tests can measure the vulnerability of an integrated circuit to ESD. The three most common test configurations are called the human body model(HBM) employs the circuit shown in Figure. k5.1DUTpF150kV2 Figure 1 Human body model When the switch is pressed, a 150pF capacitor charge

10、d to a specified voltage discharges through a 1.5K series resistor into the device under test(DUT). Ideally, each pair of pins would be independently tested for ESD susceptibility, but most testing regimens only specify a limited number of pin combinations to reduce test time. Each pair of pins is s

11、ubjected to a series of positive and negative pulses； for example, three positive and three negative. After ESD stressing is complete, the part is tested to see if it still meets electrical specifications. Modern integrated circuits are routinely expected to survive 2KV HBM. Specific pins on certain

12、 parts may be required to survive up 25KV HBM. Figure shows the circuit employed for the machine model(MM). A 200pF capacitor charged to a specified voltage discharges through a 0.5H series inductance into the DUT. As in the HBM test, each pin combination is subjected to a predetermined series of po

13、sitive and negative pulses.with only a small inductance to limit the peak current, the machine model forms a much harsher test than the human body model. New parts can survive more than 500V under machine model testing. H5.0DUTpF200 Figure 2 Machine model A third ESD test called the charged device m

14、odel(CDM) is gradually replacing the machine model. The charged device model places the integrated circuit package upside-down on a grounded metal plate and then charges the devices to a specified voltage through a high-value resistor. A special probe then discharges one pin to a low-impedance groun

15、d. Researchers believe that this procedure more accurately model factory handling conditions than either the human body or the machine model. CDM testing produces very brief pulses of extremely high current. A typical testing regimen will specify 1 to 1.5KV CDM testing. Effects Electrostatic discharge causes several different forms of electrical damage, including dielectric rupture, dielectric degradation, and avalanche-induced junction leakage. In extreme cases, ESD discharges can even vaporize metallization or shatter the bulk silicon.