外文翻译---三星S3C2442B 32位精简指令应用处理器用户手册

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1、天津工程师范学院 2007 届本科生毕业设计 1 英文资料 S3C2442B 32-BIT RISC APPLICATION PROCESSOR USERS MANUAL INTRODUCTION This users manual describes SAMSUNGs SC32442B 16/32-bit RISC microprocessor. SAMSUNGs SC32442B is designed to provide hand-held devices and general applications with low-power, and high-performance mic

2、ro-controller solution in small die size. To reduce total system cost, the SC32442B includes the following components. The SC32442B is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for co

3、st- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The SC32442B offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA

4、BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length. By providing a complete set of common system peripherals, the SC32442B minimizes overall system costs and eliminates the need to configure additional components. The integrated o

5、n-chip functions that are described in this document include: Around 400MHz1.5V arm and 1.5V internal, 300MHz1.35V arm and 1.35V internal, 1.8Vmemory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-Cache/MMU External memory controller (SDRAM Control and Chip Select logic) LCD controller (

6、up to 4K color STN and 256K color TFT) with LCD-dedicated DMA 4-ch DMA controllers with external request pins 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO) 2-ch SPls IIC bus interface (multi-master support) IIS Audio CODEC interface SD Host interface version 1.0 & MMC Protocol version 2

7、.11 compatible 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1) 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer 8-ch 10-bit ADC and Touch screen interface RTC with calendar function Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for sc

8、aling) 130 General Purpose I/O ports / 24-ch external interrupt source 天津工程师范学院 2007 届本科生毕业设计 2 Power control: Normal, Slow, Idle, stop and Sleep mode On-chip clock generator with PLL FEATURES Architecture Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC arch

9、itecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports

10、 the ARM debug architecture. Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB). System Manager Little/Big Endian support. Support Fast bus mode and Asynchronous bus mode. Address space: 128M bytes for each bank (total 1G bytes). Supports programmable 8/16/32-bit data bus w

11、idth for each bank. Fixed bank start address from bank 0 to bank 6. Programmable bank start address and bank size for bank 7. Eight memory banks: Six memory banks for ROM, SRAM, Two memory banks for ROM/SRAM/ Synchronous DRAM. Complete Programmable access cycles for all memory banks. Supports extern

12、al wait signals to expand the bus cycle. Supports self-refresh mode in SDRAM for power-down. Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). NAND Flash Boot Loader Supports booting from NAND flash memory. 4KB internal buffer for booting. Supports storage memory for NA

13、ND flash memory after booting. Supports Advanced NAND flash Cache Memory 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). 8words length per line with one valid bit and two dirty bits per line. Pseudo random or round robin replacement algorithm. Write-through or write-back cache operation to update the main memory. The write buffer can hold 16 words of data and four addresses. Clock & Power Manager On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400MHz1.5V arm and 1.5V internal,