外文翻译---语言概观

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1、附录 4 英文资料及译文 1 英文资料 (From DIGITAL DESIGN principles & practices ,John F. Wakerly) Language Overview What is VHDL? VHDL is a programming language that has been designed and optimized for describing the behavior of digital systems. VHDL has many features appropriate for describing the behavior of elec

2、tronic components ranging from simple logic gates to complete microprocessors and custom chips. Features of VHDL allow electrical aspects of circuit behavior (such as rise and fall times of signals, delays through gates, and functional operation) to be precisely described. The resulting VHDL simulat

3、ion models can then be used as building blocks in larger circuits (using schematics, block diagrams or system-level VHDL descriptions) for the purpose of simulation. VHDL is also a general-purpose programming language: just as high-level programming languages allow complex design concepts to be expr

4、essed as computer programs, VHDL allows the behavior of complex electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. Like Pascal, C and C+, VHDL includes features useful for structured design techniques, and offers a rich set of control an

5、d data representation features. Unlike these other programming languages, VHDL provides features allowing concurrent events to be described. This is important because the hardware described using VHDL is inherently concurrent in its operation. One of the most important applications of VHDL is to cap

6、ture the performance specification for a circuit, in the form of what is commonly referred to as a test bench. Test benches are VHDL descriptions of circuit stimuli and corresponding expected outputs that verify the behavior of a circuit over time. Test benches should be an integral part of any VHDL

7、 project and should be created in tandem with other descriptions of the circuit. A standard language One of the most compelling reasons for you to become experienced with and knowledgeable in VHDL is its adoption as a standard in the electronic design community. Using a standard language such as VHD

8、L virtually guarantees that you will not have to throw away and recapture design concepts simply because the design entry method you have chosen is not supported in a newer generation of design tools. Using a standard language also means that you are more likely to be able to take advantage of the m

9、ost up-to-date design tools and that you will have access to a knowledge base of thousands of other engineers, many of whom are solving problems similar to your own. A brief history of VHDL VHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, was developed

10、 in the early 1980s as a spin-off of a high-speed integrated circuit research project funded by the U.S. Department of Defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit de

11、sign problems that involved multiple teams of engineers. With only gate-level design tools available, it soon became clear that better, more structured design methods and tools would be needed. To meet this challenge, a team of engineers from three companies ?IBM, Texas Instruments and Intermetrics

12、?were contracted by the Department of Defense to complete the specification and implementation of a new, language-based design description method. The first publicly available version of VHDL, version 7.2, was released in 1985. In 1986, the Institute of Electrical and Electronics Engineers, Inc. (IE

13、EE) was presented with a proposal to standardize the language, which it did in 1987 after substantial enhancements and modifications were made by a team of commercial, government and academic representatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every simulation and syn

14、thesi product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features to their products. Although IEEE Standard 1076 defines the complete VHDL language, there are aspects of th

15、e language that make it difficult to write completely portable design descriptions (descriptions that can be simulated identically using different vendors?tools). The problem stems from the fact that VHDL supports many abstract data types, but it does not address the simple problem of characterizing

16、 different signal strengths or commonly used simulation conditions such as unknowns and high-impedance. Soon after IEEE 1076-1987 was adopted, simulator companies began enhancing VHDL with new, non-standard types to allow their customers to accurately simulate complex electronic circuits. This cause

17、d problems because design descriptions entered into one simulator were often incompatible with other simulation environments. VHDL was quickly becoming a nonstandard. To get around the problem of nonstandard data types, another standard was developed by an IEEE committee. This standard, numbered 116

18、4, defines a standard package (a VHDL feature that allows commonly used declarations to be collected into an external library) containing definitions for a standard nine-valued data type. This standard data type is called std_logic, and the IEEE 1164 package is often referred to as the Standard Logi

19、c package. The IEEE 1076-1987 and IEEE 1164 standards together form the complete VHDL standard in widest use today. (IEEE 1076-1993 is slowly working its way into the VHDL mainstream, but it does not add significant new features for synthesis users.) Standard 1076.3(often called the Numeric Standard

20、 or Synthesis Standard) defines standard packages and interpretations for VHDL data types as they relate to actual hardware. This standard, which was released at the end of 1995, is intended to replace the many custom (nonstandard) packages that vendors of synthesis tools have created and distribute

21、d with their products. IEEE Standard 1076.3 does for synthesis users what IEEE 1164 did for simulation users: increase the power of Standard 1076, while at the same time ensuring compatibility between different vendors?tools. The 1076.3 standard includes, among other things: 1) A documented hardware

22、 interpretation of values belonging to the bit and boolean types defined by IEEE Standard 1076, as well as interpretations of the std_ulogic type defined by IEEE Standard 1164. 2) A function that provides don&care or wild card testing of values based on the std_ulogic type. This is of particular use for synthesis, since it is often helpful to express logic in terms of don 抰 care values.