外文翻译-----单片机数据采集接口

《外文翻译-----单片机数据采集接口》由会员分享，可在线阅读，更多相关《外文翻译-----单片机数据采集接口（9页珍藏版）》请在毕设资料网上搜索。

1、附录二 外文原文及翻译 Single-Chip Data Acquisition Interface Gintaras Paukstaitis Abstract This paper presents a single-chip data acquisition interface. Its devoted for from one to eight analogous signals input to RAM of IBM PC or compatible computers. Maximal signal sampling rate is 80 kHz. Interface has pro

2、grammable gain for analogous signals as well as programmable sampling rate and number of channels. Some functional unit was designed using synthesis from VHDL with help of Synopsys. Interface was based on 1 mm CMOS process from ATMEL-ES2. It was verified using kit for DFWII of Cadence. The Place & R

3、oute tools from Cadence have been used to obtain the circuit layout. Table of contains Abstract 1. Introduction 2. Steps of Designing 3. Analogous Part 4. Digital Part 5. Interface Testing 6. Creation of Layout 7.Technical Data 8. Conclusions 9. Acknowledgements 10.References 1. Introduction Nowaday

4、s units with VLSI are widely used in the world. It is really important for miniaturisation. Circuits with some IC redesigned to VLSI reduce its area many times. By the way, relatively VLSI itself becomes cheaper. While using units with VLSI gets less damage, as well as uses less power. Using of CAD

5、makes easier and faster complicated IC designing. Cheaper computers give an opportunity to get servers not only for big companies and institutions of education but also for medium firms. This stride encouraged such complex circuits designing programs as Synopsys and Cadence creation. While using the

6、m it is possible to design suitable circuits for fabrication or layout creation. Synopsys simulates functions described in VHDL and from its description synthesises circuits which can be made from Cadence libraries elements. It abounds to transform them to Cadence and to create the layout of IC. The

7、 steps of Cadence designing are illustrated in Fig. 1. Single-chip data acquisition interface was designed according to basic circuit of data acquisition board. It was designed by Department of Applied Electronics in Kaunas University of Technology. It is used in medicine. Created single-chip interf

8、ace has better electrical parameters. Thats way it could be used wider. Prototype board was designed in TTL element base. Single-chip interface is designed in CMOS element base. While converting the circuit there were no complicated problems. The delay of CMOS elements is less than TTL. Thats way th

9、e delay of signals was not bigger and didnt change the first work of the circuit. ISA bus signals of IBM PC are TTL element logic levels, therefore interface should be connected through buffers for TTL and CMOS logic levels reconciliation. 2. Steps of Designing A circuit was designed according to a

10、basic circuit. That is way Semi-Custom Design method was used. The flow-chart of interface is shown in the Fig. 2. It was necessary to use 8 operational amplifiers (OA) to fit eight analogous signals to A/D converters limits. OA has programmable established gain. In many cases it could let analogous

11、 signal without any additional amplifiers to give to A/D converters. Gain for every OA separately fixed with Gain Control Block. Two converters change analogous signal to the digital one. Each of converters has 4 switch-able inputs. Converters work method is comparison of every bit. Channel Control

12、Block establishes the order of signal switching. Programmable interval timer establishes the frequency on signal switching as well as the data sampling rate. It has three counters, which work in frequency dividing and one-shot modes. Dividing coefficients of timer is settings through Internal Bus. T

13、he length of dividing coefficient is 16 bits. The timer divides 894kHz frequency signal therefore minimal interface sampling rate is FMIN = 894 / 216 = 14 Hz. Maximal sampling rate limits speed characteristic of A/D converters. It is equal FMAX = 80 kHz. Gain of OA, sampling rate and number of switc

14、hing channels is set while sending charging words to the ports which are established by Address Decoding Block. Data to PC is fed in a single Direct Memory Access (DMA) mode. DMA controller is in charge of commuting protocol from PC. DMA Control Block is responsible from the side of interface. Clock

15、 Signal Block sets clock frequency of 1,8 MHz for converters and 0,9 MHz for timer. Control logic consists of simple gates and flip-flops. That is way gates and Flip-flops of the ES2 1mm CMOS elements library was used to design it. The reason why the 1mm CMOS ES2 technology library was chosen was th

16、e wide choice of its analogous elements for Semi-Custom Design. But ES2 library has no some functional elements which were used in the circuit. For example Intel 8253 programmable interval timer, binary counter or address decoder. Therefore these elements was described in VHDL. While using elements

17、of 1mm CMOS ES2 technology library with the assistance of Synopsys necessary circuits ware synthesised. EDIF of circuits was transported to Cadence. Having been connected with the left control logic and with the analogous signals converting part they made a full functioning interface. The stages of

18、designing are shown 3. Analogous Part Alternating analogous voltage signals are changed to pulsate one from 0 to +5 V signal in the analogous part of interface. As converter is made of CMOS elements and its power supply is 0 and +5 V so it can change only signal between 0 and +5 V limits. In order t

19、o reduce converting mistake converters are given analogous signal which should as close as possible to the limits. Programmable OA makes stronger analogous signals. It has 16 possible gains which are selected with the help of four bit code. They have non-inverting input which has a pad for external

20、analogous signal input. To change the alternating voltage ( 2,5 V) to pulsate one (0 to +5 V) virtual ground pad of OA is connected with +2,5 V and signal source ground (its ground voltage must be 2,5 V). Design of interface was simulated with Verilog-XL program. It simulates only digital signals. T

21、hat is way while simulating analogous signals they were described as 8-bit digital vectors. Verilog HDL models of analogous elements are used for this simulation. HDL models are changed into layout models for the creation of layout. A/D converter of ES2 library is divided into 2 parts: analogous par

22、t consist of D/A converter and comparator. There is control logic and registers in the digital part. That is way only analogous part is changed in converters when layout is being created. 4. Digital Part Control Block of interface was designed while changing discrete components of board to according

23、ly chip components of ES2 library. Some changes through different control of ES2 library and prototype board analogous elements were made. It was timer described in VHDL for its designing. Three models were created: two models for clock frequency dividing from coefficient which length is 16 and 8 bi

24、t and another one for one-shot mode. The length of control word is 8 bit. Standard packages of IEEE library were used for description of the models. It made easier operations themselves with vector data. VHDL models were simulated with Synopsys VHDL Debugger. Functional correct VHDL models of timer

25、counters were synthesised by using elements of ES2 library. While synthesisingoptimisation was done. Because the delay of circuits signal (few nanoseconds) is comparing with clock period (1,2 mm) is less so optimisation was only worth for small areas. Set_max_area command was used for this goal. The

26、 area rapport summary of 16 bits timer counter synthesis is shown in the Table 1. It is clear that a number of counters elements becomes smaller approximately for 13%. But their area becomes smaller only for 1,5%. The reason is that the number of elements was being diminished with diminishing of combinational logic. While element of combinational logic comparing with noncombinational one