电气电子专业毕业设计外文翻译--用SPMC75的PDC定时器做BLDC电机的速度检测

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1、 XXXX 大学 （ 外文翻译材料 ） 学院： 专业： 学生姓名： 指导教师： 外文翻译（原文） 1 BLDC Motor Speed Estimation Using PDC Timer Module 1 Speed Calculation of BLDC 1.1 Summary of BLDC Since current BLDC has substituted the electrical commutator for the mechanical one, it eliminates the disadvantages of noise, spark, electromagnetic

2、disturbance, short lifetime, etc. Now BLDC is provided with advantages of simple structure, dependable operation and easy maintenance as AC motor does, as well as advantages of high efficient, no excitation cost and functional speed regulation as traditional DC motor does. So it is widely used in va

3、rious fields of industrial control now. 1.2 PDC Module Introduction SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC) timers used for capture function and PWM operation. It also supports position detection features for Brushless-DC motor application. The PDC timers are

4、very suitable for both mechanical speed calculation, with ACI and BLDC motor included, and phase commutation for changing current conduction according to position information. Figure 1-1 shows the block diagram of entire PDC timers, channel 0 and channel 1. For details of PDC timers specification, p

5、lease refer to Table 1-1. Table 1-1 PDC Timer Function PDC Timer 0 PDC Timer 1 Clock sources Internal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKB Internal clock: FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 External clock: TCLKA, TCLKB IO pins TIO0A, TIO0B,

6、 TIO0C TIO1A, TIO1B, TIO1C Timer general register P_TMR0_TGRA, P_TMR0_TGRB, P_TMR0_TGRC P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC Timer buffer register P_TMR0_TBRA, P_TMR0_TBRB, P_TMR0_TBRC P_TMR1_TBRA, P_TMR1_TBRB, P_TMR1_TBRC Timer period and counter register P_TMR0_TPR, P_TMR0_TCNT P_TMR1_TPR, P_TMR1

7、_TCNT 外文翻译（原文） 2 Capture sample clock Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Counting edge Count on rising, falling, both edge Count on rising, falling, both edge Counter clear source Cleared on P_TMR0_TGRA, P_TMR0_TGRB, P_TMR0_TGRC capture input. Clear

8、ed on P_POS0_DectData position detection data changes. Cleared on P_TMR0_TPR compare matches. Cleared on P_TMR1_TGRA, P_TMR1_TGRB, P_TMR1_TGRC capture input. Cleared on P_POS1_DectData position detection data changes. Cleared on P_TMR1_TPR compare matches. Input capture function Yes Yes PWM compare

9、match output function 1 output Yes Yes 0 output Yes Yes Output Hold Yes Yes Edge-aligned PWM Yes Yes Center-aligned PWM Yes Yes Phase counting mode Yes, phase inputs are TCLKA/TCLKB Yes, phase inputs are TCLK C/TCLKD Timer buffer operation Yes Yes AD convert start trigger P_TMR0_TGRA compare match P

10、_TMR1_TGRA compare match Interrupt sources Timer 0 TPR interrupt Timer 0 TGRA interrupt Timer 0 TGRB interrupt Timer 0 TGRC interrupt Timer 0 PDC interrupt Timer 0 overflow interrupt Timer 0 underflow interrupt Timer 1 TPR interrupt Timer 1 TGRA interrupt Timer 1 TGRB interrupt Timer 1 TGRC interrupt Timer 1 PDC interrupt Timer 1 overflow interrupt Timer 1 underflow interrupt