毕设外文翻译--单片机基础

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1、 毕业设计（论文）外文资料翻译 系别： 电气系 专业： 电气工程及其自动化 班级： 姓名： 学号： 外文出处： Atomation Professional English Course （用外文写） Pressed By Machinery Industry Press 附 件： 1、外文原文； 2、外文资料翻译译文。 指导教师评语： 签字： 年 月 日 注：请将该封面与附件装订成册。 1、 外文原文（复印件） A: Fundamentals of Single-chip Microcomputer Th e si n gle - chip m icr o com pu t er i s t

2、h e cul min atio n o f b oth t he d ev el opm ent o f th e di git al co mp ut er an d th e in t egr at ed cir cui t argu abl y t h e t o w m os t s i gni fi can t in vent io ns o f the 20 th cent u r y 1 . Th es e t ow t yp es o f ar chit ect u r e are f ou nd i n s in gl e - ch ip m icr o com pu t

3、er. S om e emp lo y t h e sp lit p r o gr am/ d at a m em o r y o f th e H ar vard ar chi t ectu r e, s ho w n in Fi g. 3 -5A-1 , other s f oll o w th e ph ilo so ph y, w i d el y ad apt ed fo r gen er al - p u rp os e com put er s and mi cr op ro cess or s , o f m aki n g n o l o gical dis tin ctio

4、 n b etw een pr o gr am an d d at a m em or y as i n th e P r in cet on ar chi t ectu r e, s ho w n in Fi g. 3 -5A-2. In gen er al t erms a si n gl e - ch ip mi cr o comp ut er is ch aract eriz ed b y t h e i n co r po r ati on of al l th e un its o f a co mp ut er i nt o a si ngl e d evi ce, as s h

5、o w n i n Fi g3 -5A-3. Fig.3-5A-1 A Harvard type Fig.3-5A-2. A conventional Princeton computer Program memory Data memory CPU Input& Output unit memory CPU Input& Output unit Reset Interrupts Power Fig3-5A-3. Principal features of a microcomputer Read only memory (ROM).R O M i s us uall y f o r the

6、p erm an ent, non- vo l atil e st o r age o f an ap pl icatio ns p r o gr am . M an y mi cro com put er s an d m icr o co nt ro ll ers are int end ed f or h i gh - v ol um e appl i cati on s and h en ce t h e eco no mi cal m an uf act ur e o f th e d evi ces r eq ui r es th at t h e co nt en ts o f

7、th e p r o gr am m emo r y b e commi tt ed p erm anen tl y d u r in g t h e m an u f actu r e o f chi ps . Cl earl y, t hi s imp li es a ri go r ou s app ro ach t o R O M co d e d ev elo pm en t sin ce ch an ges can no t b e m ad e aft er manu f act u re . T his d ev elo pm ent p ro ces s m ay i nv

8、ol ve em ul at io n u si n g a so p h ist icated dev el opm ent s ys tem w it h a h ard w ar e em ul ati on cap abili ty as w ell as th e us e o f po w er ful s o ft war e t oo ls . S om e m an uf actu r ers p r ov id e add iti on al R OM o pti on s b y i n cl ud in g i n th ei r r an ge d evices w

9、it h (o r in t en ded fo r us e wit h) u ser p ro gr am m abl e m em o r y. T h e sim ples t of t h es e is u su al l y d ev i ce wh ich can op er at e in a m icr op r ocess o r m od e b y u s in g som e of th e in pu t/o ut put li n es as an add r es s an d d at a bu s f o r acces sin g ex t ern al

10、 mem or y. T h is t yp e o f d ev i ce can b eh av e f u n cti on al l y as t h e s in gl e chi p mi cro co m pu ter f rom w hi ch i t is d eri v ed al beit w it h r es t ri ct ed I/ O an d a m odi fi ed ex ter n al ci r cu it. Th e us e o f th es e R OM l ess d evi ces is comm on ev en in pr o du c

11、t io n ci r cuit s w h er e th e v olu me d o es n ot ju sti f y t h e d ev elo pm en t co st s o f cust om o n -chi p R OM 2 ；t her e can stil l be a si gni fi cant s avin g in I/ O an d o th er chi ps com p ared t o a co nv enti on al mi crop r o cess o r b as ed circu it. Mo r e ex act r ep l acem ent f or R OM d evi ces can b e o bt ai n ed in t h e fo r m of v ari an ts w ith pi ggy - b ack External Timing components System clock Timer/ Counter Serial I/O Prarallel I/O RAM ROM CPU