有关A D（模数)转换的外文翻译

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1、ICL7135 4 1/2 Digit, BCD Output, A/D Converter The Intersil ICL7135 precision A/D converter, with its multiplexed BCD output and digit drivers, combines dual-slope conversion reliability with +1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM market. The 2.0000V full sc

2、ale capability, auto-zero, and auto-polarity are combined with true ratiometric operation, almost ideal differential linearity and true differential input. All necessary active devices are contained on a single CMOS lC, with the exception of display drivers, reference, and a clock. The ICL7135 bring

3、s together an unprecedented combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10 V, zero drift of less than 1V/ , input bias current of 10pA (Max), and rollover error of less than one count. The versatility of multiplexed BCD outputs is increased by the

4、addition of several pins which allow it to operate in more sophisticated systems. These include STROBE , OVERRANGE , UNDERRANGE , RUN/HOLD and BUSY lines, making it possible to interface the circuit to a microprocessor or UART. Features * Accuracy Guaranteed to+1 Count Over Entire 20000 Counts (2.00

5、00V Full Scale) * Guaranteed Zero Reading for 0V Input * 1pA Typical Input Leakage Current * True Differential Input * True Polarity at Zero Count for Precise Null Detection * Single Reference Voltage Required * Over range and Under range Signals Available for Auto-Range Capability * All Outputs TTL

6、 Compatible * Blinking Outputs Gives Visual Indication of Over range * Six Auxiliary Inputs/Outputs are Available for Interfacing to UARTs , Microprocessors, or Other Circuitry * Multiplexed BCD Outputs * Pb-Free Available (RoHS Compliant) Detailed Description Analog Section Each measurement cycle i

7、s divided into four phases. They are (1) auto-zero (AZ), (2) signal-integrate (INT), (3) de-integrate (DE) and (4) zero-integrator (Zl). Auto-Zero Phase During auto-zero, three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, th

8、e reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is

9、limited only by the noise of the system. In any case, the offset referred to the input is less than 10V. Signal Integrate Phase During signal integrate , the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter

10、 then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range； within one volt of either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied

11、to analog COMMON to establish the correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is latched into the polarity F/F. De-Integrate Phase The third phase is de-integrate or reference integrate. Input low is internally connected to analog COMMON and input hig

12、h is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the out- put to return to zero is proportional to the input signa

13、l. Specifically the digital reading displayed is: Zero Integrator Phase The final phase is zero integrator. First, input low is shorted to analog COMMON. Second, a feedback loop is closed around the system to input high to cause the integrator output to return to zero. Under normal condition, this p

14、hase lasts from 100 to 200 clock pulses, but after an over range conversion, it is extended to 6200 clock pulses. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier； or specifically from 0.5V below the positive supply to 1V abov

15、e the negative supply. In this range the system has a CMRR of 86dB typical. However, since the integrator also swings with the common mode voltage, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common-mode voltage with a ne

16、ar full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the recommended 4V full scale swin

17、g with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. Analog COMMON Analog COMMON is used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system an

18、d is taken care of by the excellent CMRR of the converter. However, in most applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus remo ving the common mode voltage from the converter. The

19、reference voltage is referenced to analog COMMON. Reference The reference input must be generated as a positive voltage with respect to COMMON, Digital Section Figure 5 shows the Digital Section of the ICL7135. The ICL7135 includes several pins which allow it to operate conveniently in more sophisti

20、cated systems. These include: Run/HOLD (Pin 25) When high (or open) the A/D will free-run with equally spaced measurement cycles every 40,002 clock pulses. If taken low, the converter will continue the full measurement cycle that it is doing and then hold this reading as long as R/H is held low. A short positive