X5045带4Kb SPI EEPROM 的CPU监控器中英文翻译

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1、 1 附 录 英文文献 4K X5043/X5045 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM DESCRIPTION These devices combine four popular functions, Poweron Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduc

2、es board space requirements, and increases reliability. Applying power to the device activates the power on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an i

3、ndependent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after

4、cycling the power. The devices low VCC detection circuitry protects the users system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thr

5、esholds are available, however, Xicors unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Xicors block lock protection. The a

6、rray is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Xicors proprietary Direct Write cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of

7、 100 years. FEATURES Selectable time out watchdog timer Low VCC detection and reset assertion Five standard reset threshold voltages Re-program low VCC reset threshold voltage using special programming sequence. Reset signal valid to VCC= 1V Long battery life with low power consumption 50A max stand

8、by current, watchdog on 2 10A max standby current, watchdog off 2mA max active current during read 2.7V to 5.5V and 4.5V to 5.5V power supply versions 4Kbits of EEPROM1M write cycle endurance Save critical data with Block Lock memory Protect 1/4, 1/2, all or none of EEPROM array Built-in inadvertent

9、 write protection Write enable latch Write protect pin 3.3MHz clock rate Minimize programming time 16-byte page write mode Self-timed write cycle 5ms write cycle time (typical) SPI modes (0,0 & 1,1) Available packages 8-lead MSOP, 8-lead SOIC, 8-pin PDIP 14-lead TSSOP PIN DESCRIPTIONS Serial Output

10、(SO) SO is a push/pull serial data output pin. During a readcycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin.

11、 Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the fallin

12、g edge of the clock input. Chip Select (CS) When CS is high, the X5043/45 is deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043/45 will be in the standby power mode. CS low enables the X5043/45, placing it in the active power mode. It

13、 should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043/45 are disabled, but the part otherwise functions normally.When WP is held high, all functions, including non volat

14、ile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043/45. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043/45, RESET/RESET is an active low/HIGH,open drain output which goes a

15、ctive whenever VCC falls below the minimum VCCsense level. It will remain active until VCC rises 3 above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of

16、CS will reset the watchdog timer. PRINCIPLES OF OPERATION Power On Reset Application of power to the X5043/X5045 activates a Power On Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insuf-ficient voltage or pr

17、ior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms(nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043/X5045 monitors the VCC level and asserts RESET/RESET if supply volta

18、ge falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer

19、 The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. T

20、he state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. VCC Threshold Reset Procedure The

21、 X5043/X5045 is shipped with a standard VCCthreshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043/X5045 threshold may be

22、 adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make

23、the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN

24、 command,followed by a write of Data 00h to address 01h.CS going HIGH on the write operation initiates the VTRIP programmingsequence. Bring WP LOW to complete the operation. Note:This operation also writes 00h to array address 01h. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a native voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is