单片机外文翻译3

《单片机外文翻译3》由会员分享，可在线阅读，更多相关《单片机外文翻译3（10页珍藏版）》请在毕设资料网上搜索。

1、外文及翻译 英文资料 : STC89C51（ 8-bit Micro controller with 4K Bytes Flash） The STC89C51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytesof In-System Programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with t

2、he industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89C51 is a powerf

3、ul microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. Features： Compatible with MCS.-51 Products 4K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operati

4、on: 0 Hz to 33 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Full Duplex UART Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Watchdog Timer Dual Data Pointer Power-off

5、 Flag Fast Programming Time Flexible ISP Programming (Byte and Page Mode) Green (Pb/Halide-free) Packaging Option The STC89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-

6、level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the STC89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,

7、timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. VCC： Supply voltage (all packages except 42-PDIP). GND： Ground (al

8、l packages except 42-PDIP； for 42-PDIP GND connects only the logic core and the embedded program memory). VDD： Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory. PWRVDD： Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The applic

9、ation board MUST connect both VDD and PWRVDD to the board supply voltage. PWRGND： Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and

10、PWRGND to the board ground. Port 0： Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/d

11、ata bus during accesses to external program and data memory. In this mode, PO has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1： Port 1 is an 8

12、-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current

13、 (lip) because of the internal pull-ups. Port 2： Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port

14、2 pins that are externally being pulled low will source current (lip) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVXDPTR). In this application, Port 2

15、uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVXRI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verificatio

16、n. Port 3： Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the STC89C51， as shown in the following table. RST：