DS1820 单总线数字温度计外文翻译

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1、 1 外文资料 DS18B20 Programmable Resolution 1-Wire Digital Thermometer The DS18B20 Digital Thermometer provides 9 to 12-bit (configurable) temperature readings which indicate the temperature of the device. Information is sent to/from the DS18B20 over a 1-Wire interface, so that only one wire (and ground

2、) needs to be connected from a central microprocessor to a DS18B20. Power for reading, writing, and performing temperature conversions can be derived from the data line itself with no need for an external power source. Because each DS18B20 contains a unique silicon serial number, multiple DS18B20s c

3、an exist on the same 1-Wire bus. This allows for placing temperature sensors in many different places. Applications where this feature is useful include HVAC environmental controls, sensing temperatures inside buildings, equipment or machinery, and process monitoring and control. The block diagram o

4、f Figure 1 shows the major components of the DS18B20. The DS18B20 has four main data components: 1) 64-bit laser ROM, 2) temperature sensor, 3) nonvolatile temperature alarm triggers TH and TL, and 4) a configuration register. The device derives its power from the 1-Wire communication line by storin

5、g energy on an internal capacitor during periods of time when the signal line is high and continues to operate off this power source during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply. As an alternative, the DS18B20 may also be powered from an

6、external 3V - 5.5V supply. Communication to the DS18B20 is via a 1-Wire port. With the 1-Wire port, the memory and control functions will not be available before the ROM function protocol has been established. The master must first provide one of five ROM function commands: 1) Read ROM, 2) Match ROM

7、, 3) Search ROM, 4) Skip ROM, or 5) Alarm Search. These commands operate on the 64-bit laser ROM portion of each device and can single out a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. After a ROM functi

8、on sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands. One control function command instructs the DS18B20 to perform a temperature measurement. The result of this measurement

9、 will be placed in the DS18B20s scratch-pad memory, and may be read by issuing a memory function command which reads the contents of the scratchpad memory. The temperature alarm triggers TH and TL consist of 1 byte EEPROM each. If the alarm search command is not applied to the DS18B20, these registe

10、rs may be used as general purpose user memory. The scratchpad also contains a configuration byte to set the desired resolution of the temperature to digital conversion. Writing TH, TL, and the configuration byte is done using a memory function command. Read access to these registers is through the s

11、cratchpad. 2 All data is read and written least significant bit first. The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power whenever the DQ or VDD pins are high. DQ will provide sufficient power as long as the specified timing and voltage requirements are

12、met (see the section titled “1-Wire Bus System”). The advantages of parasite power are twofold: 1) by parasiting off this pin, no local power source is needed for remote sensing of temperature, and 2) the ROM may be read in absence of normal power. In order for the DS18B20 to be able to perform accu

13、rate temperature conversions, sufficient power must be provided over the DQ line when a temperature conversion is taking place. Since the operating current of the DS18B20 is up to 1.5 mA, the DQ line will not have sufficient drive due to the 5k pull up resistor. This problem is particularly acute if

14、 several DS18B20s are on the same DQ and attempting to convert simultaneously. There are two ways to assure that the DS18B20 has sufficient supply current during its active conversion cycle. The first is to provide a strong pull up on the DQ line whenever temperature conversions or copies to the E2

15、memory are taking place. This may be accomplished by using a MOSFET to pull the DQ line directly to the power supply as shown in Figure 2. The DQ line must be switched over to the strong pull up within 10 us maximum after issuing any protocol that involves copying to the E2 memory or initiates tempe

16、rature conversions. When using the parasite power mode, the VDD pin must be tied to ground. Another method of supplying current to the DS18B20 is through the use of an external power supply tied to the VDD pin, as shown in Figure 3. The advantage to this is that the strong pull up is not required on

17、 the DQ line, and the bus master need not be tied up holding that line high during temperature conversions. This allows other data traffic on the 1-Wire bus during the conversion time. In addition, any number of DS18B20s may be placed on the 1-Wire bus, and if they all use external power, they may a

18、ll simultaneously perform temperature conversions by issuing the Skip ROM command and then issuing the Convert T command. Note that as long as the external power supply is active, the GND pin may not be floating. The use of parasite power is not recommended above 100 C, since it may not be able to s

19、ustain communications given the higher leakage currents the DS18B20 exhibits at these temperatures. For applications in which such temperatures are likely, it is strongly recommended that VDD be applied to the DS18B20. For situations where the bus master does not know whether the DS18B20s on the bus

20、 are parasite powered or supplied with external VDD, a provision is made in the DS18B20 to signal the power supply scheme used. The bus master can determine if any DS18B20 are on the bus which require the strong pull up by sending a Skip ROM protocol, then issuing the read power supply command. Afte

21、r this command is issued, the master then issues read time slots. The DS18B20 will send back “0” on the 1-Wire bus if it is parasite powered； it will send back a “1” if it is powered from the VDD pin. If the master receives a “0,” it knows that it must supply the strong pull up on the DQ line during

22、 temperature conversions. See “Memory Command 3 Functions” section for more detail on this command protocol. The DS18B20 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56-bits of the 64-bit ROM and compare it to the value

23、 stored within the DS18B20 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: 1458 XXXCRC The DS18B20 also generates an 8-bit CRC value using the same polynomial function shown above and provides this value to the bus maste

24、r to validate the transfer of data bytes. In each case where a CRC is used for data transfer validation, the bus master must calculate a CRC value using the polynomial function given above and compare the calculated value to either the 8-bit CRC value stored in the 64-bit ROM portion of the DS18B20

25、(for ROM reads) or the 8-bit CRC value computed within the DS18B20(which is read as a ninth byte when the scratchpad is read). The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry inside the DS18B20 that prevents a c

26、ommand sequence from proceeding if the CRC stored in or calculated by the DS18B20 does not match the value generated by the bus master. The 1-Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 6. Additional information about the Dal

27、las 1-Wire Cyclic Redundancy Check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch Memory Products.” The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s.