VHDL语言设计数字系统的外文翻译
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1、DESIGNING A DIGITAL SYSTEM WITH VHDL Valentina Stoyanova Kukenska Abstract: In this paper a digital system designing with VHDL is presented. Here are exposed sequentially all the phases of the very digital systems designing. The main methods are also on show here. The project descriptions types are
2、presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models. For creating the project of the chosen digital system an integrated system WebPack was used, as well as ModelSIm XE II for the models simulation. Keywords: Design, VHDL, digital systems, model, WebPack
3、 1. INTRODUCTION The digital systems are complex ones, consisting of lots of components. As far as the automated design of such systems is concerned, methods for designing time reducing and limiting the complexity of the task are sought out and applied. A method of the kind is connected with the dec
4、omposition and hierarchy principles. The decomposition of the systems is realized in a way, which differentiates functionally independent modules. A digital system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inp
5、uts. One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals. This kind of description is called a structural description. In many cases, it is n
6、ot appropriate to describe a module structurally. One such case is a module, which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC.
7、 In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description. Usually, for structural and behavioral description, either Verilog or VHDL is used. In this pape
8、r a designing with VHDL is presented. Here are exposed sequentially all the phases of the very digital systems designing. The main methods are also on show here. The project descriptions types are presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models. Here
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