1、此文档是毕业设计外文翻译成品（ 含英文原文+中文翻译），无需调整复杂的格 式！下载之后直接可用，方便快捷！本文价格不贵,也就几十块钱！一辈子也就 一次的事！ 外文标题：Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions 外文作者： G. Edward Suh, Charles W. O Donnell, Ishan Sachdev, and Srinivas Devadas 文献出处: International Symposium on Comp
2、uter Architecture (ISCA05)， 2005 (如觉得年份太老，可改为近 2 年，毕竟很多毕业生都这样做) 英文 9169 单词，49797 字符，中文 15005 汉字。 Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions ABSTRACT:Secure processors enable new applications by ensuring private and authentic program execution
3、even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physical Random Functions, we propose a new way of reliably protecting and sharing secrets that is more secure than existing solutions based o
4、n non-volatile memory. Our architecture gives applications the flexibility of trusting and protecting only a portion of a given process, unlike prior proposals which require a process to be protected in entirety. We also put forward a specific model of how secure applications can be programmed in a
5、high-level language and compiled to run on our system. Finally, we evaluate a fully functional FPGA implementation of our processor, assess the implementation tradeoffs, compare performance, and demonstrate the benefits of partially protecting a program. 1.INTRODUCTION As computing devices become ub
6、iquitous, interconnectivity and interdependability are escalating the need for secure and trusted computation. Public and private data must be certified and safe-guarded while still allowing operating systems and applications the flexibility and performance users demand. To further complicate matters, the proliferation of embedded, portable devices is creating security risks which software-only solutions cannot handle. Even large-scale software security efforts can suffer from a single point o
