1、第 1 页 /共 10 页 出处： Lee H H, Park W H, Ryu H G. High speed digital hybrid PLL frequency synthesizerC/ Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings. 2006. 锁相技术译文翻译 英文原名： High Speed Digital Hybrid PLL Frequency Synthesizer 译文： 高速数字 混合 锁相环频率合成器 年纪专业： 通信工程 姓名： 学号：
2、 2011 年 5 月 2 日 第 2 页 /共 10 页 英文 中文 High Speed Digital Hybrid PLL Frequency Synthesizer Abstract ： The conventional PLL(Phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL (DH-PLL) which includes the open loop str
3、ucture into the conventional PLL synthesizer has been studied to overcome this problem. It operates in high speed, but the hardware complexity and power consumption are other serious problems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characte
4、ristic of VCO (voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching spe
5、ed. Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL. Key Words: PLL, DLT, Frequency synthesis I. INTRODUCTION High speed frequency synthesis is very important and is widely used in the electronic and communication system applicati
6、ons. In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer for the high speed operation 1. 高速数字混合锁相环频率合 成器 摘要 ：传统的锁相环频率合成器需要很长的切换时间 ,因为其内在的闭环结构。 目前已经研发的一种数字混合锁相环来解
7、决这一问题 在传统的锁相环频率合成器 中加入开环结构。 它可以 高速运行， 但硬件复杂度和功耗是一个严重的问题，因为它的数字查找表（包含压控振荡器的传输特性）在 ROM 中频繁执行。 本文提出一种新的数字混合锁相环 使用一种简单的数字查找表代替复杂的 ROM 型数字查找表。 此外，定时同步电路使得环路超调量很小且建立时间短，从而保证了超高速切换速度。 同时 ,硬件复杂度和功耗 比传统的数字混合锁相环（ DH-PLL） 大约降低 28%。 关键词： 锁相环（ PLL），数值查找表（ DLT）， 频率合成 1 简介 高速频率合成是一种非常重 要的 技术 ,被广泛地应用在电子和通信系统应用。 在 1
8、999年 ,El-Ela提出在传统锁相环频率合成器压控振荡器的输入端注入额外的信号 从 D/A转换器上得到的同步锯齿波 可以使它高速度运行【 1】。 第 3 页 /共 10 页 However, it needs the optimal slope and duration at every frequency synthesis. To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design. In 2001, H. G. Ryu proposed
9、 a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the high switching speed 2. However, there is a problem that the speed of the whole system is limited by PLL. Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage
10、 converter (FVC) 3. It has a fast switching speed by the PD (phase detector), FVC using output signal of VCO and the proposed coarse tuning controller. However, H/W complexity is increased for the high switching speed. Also, it shows the fast switching characteristic only when the FVC works well. An
11、other method is pre-tuning one which is called DH-PLL in this study 4. It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of VCO(voltage con
12、trolled oscillator). For this reason, this paper proposes a timing synchronization circuit for the rapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption. Also, the requisite condition is
13、solved in the proposed method. The fast switching operation at every the frequency synthesis process is verified by the computer circuit simulation. II. DH-PLL synthesizer 但是，该锯齿波在每一次频率合成时需要最理想的斜率和持续时间。 要得到高运行速度 ,事先做好复杂设计的精确同步是必要的。 2001年 ,H.G.Ryu提出了一种简化结构的直接数字频率合成器 (DDFS)驱动的高转换速度锁相环 【 2】。 但是 ,有一个问题
14、,整个系统的速度是受锁相环 限制的。 Y.Fouzar 提出了一种使用频率 电压转换器 (FVC)具有双重回路结构的锁相环频率合成器【 3】。 因为 鉴相器 (PD)， FVC 利用了压控振荡器的输出信号和我们提出的粗调控制器 ，所以它 具有快速切换速度。 但是 ,因为有高速系统转换速度使得 H / W 的复杂性增加了。 另外，结果表明只有 FVC 工作状态良好时系统才有较高切换速度。 另一种方法是做预先调整也就是本项研究中的 DH-PLL 【 4】。 它具有高速切换的特性， 但是因为数字 查找表 (DLT)的原因， H / W 复杂度和功 耗明显增大了，因为 DLT经常被 ROM 执行， DLT 中包含 压控振荡器 (VCO)的 传输特性 。 介于以上原因 , 为得到较高切换速度和低功耗，本文提出了一种新的快速定时同步频率合成电路，用一个非常简单的 DLT替代数字逻辑块，而不用复杂的 ROM型 (DLT)。 同时 ,在该方法中所需必要条件也解决了，频率合成过程的高切换速度在计算机电路仿真中已经得到验证了。 2.DH-PLL 合成器
