1、中文 2330 字 THE MICROPROCESSOR SYSTEM A microprocessor system can be described at a number of different levels of complexity. The least complex from is that of a simple block diagram describing the interconnection and flow of information functional blocks and will be used to examine the operation of a
2、 microprocessor system. All microprocessor systems contain a central processing unit(CPU),program and data memory and input(I/O) devices.Fig.4-4 show a block diagram of a typical embedded microprocessor system in which each block corresponds roughly to the individual integrated circuit(chip) used in
3、 the system. The memory section contains both non-volatile read only memory(ROM) as program memory and volatile random access memory(RAM) as read/write data memory .For each type of memory there are a number of different types of devices ,such as erasable ROMs and static or dynamic RAMs, each of whi
4、ch is chosen for an application based on its cost and function. Four different I/O functions are shown in Fig.4-4.An analogue input channel to the microprocessor system is provided by the analogue to digital(A/D) converter and may be used to connect a device such as an analogue to digital(A/D) conve
5、rter and may be used to connect a device such as an analogue sensor. An analogue output channel is provided by the digital to analogue(D/A) converter and could be used to control an output transducer such as an electric motor, The parallel I/O device provides a number of individual lines. In output
6、mode these can be programmed to provide logic levels 1 or 0 to activate binary(on/off)devices such as lamps. In input mode it allows the microprocessor to read the state of switches and other binary devices. The serial I/O device is used to provide communications with other microprocessor systems or
7、 with an operator console used to configure the system for various operational modes. The level and power specifications of the interfacing signals of the microprocessor system are frequently incompatible with the signal specifications of the devices which are to be interfaced to it .For example, th
8、e output voltage of a D/A converter may typically be in the range 0-5 volts and be capable of supplying only a few milliamperes of current, Fig.4-4 Block diagram of a typical embedded microprocessor system while the electric motor may require a control voltage range of plus and minus 12 volts at a m
9、aximum current of 1 ampere. Consequently, additional analogue interface circuitry is often necessary to perform functions such as signal level shifting, amplification and filtering. Fig.4-4 also shows there peripheral circuits: an input control unit(ICU),a programmable counter/timer, and a direct me
10、mory access unit(DMA).All this devices are interfaced to the CPU by means of a system bus which is itself made up from an address bus and a control bus. Physically, a bus is simple a collection of parallel interconnections between to or more devices. The number of lines contained in each bus is depe
11、ndent on the type of microprocessor used in the system and the function of the bus. In Fig.4-4 we assume that the address bus has sixteen lines, the data bus has eight lines ,and the control bus contains an arbitrary number of lines depending on the control functions provided by the CPU. The concept
12、s of address and data are fundamental to the operation of a stored program computer and form a feature of all microprocessors and computers. The memory will consist of a number of memory locations capable of storing data written to them by the CPU over the data bus .Each memory location is uniquely
13、identified to the CPU by a number called its address. The CPU controls the address and control bus lines in order to write or read information to or form the memory or I/O devices. For example, if the CPU wished to write the binary number 01010101 into a memory location which had the address 0000000
14、000001111,the CPU would first place the address on to the address bus, then place the number 01010101 as data onto the data bus. Controls lines in the control bus would then be activated to cause the data to be loaded into the appropriate memory location. A similar procedure would be used if the CPU
15、 was then to read a memory address, except this the flow of data would be from the memory to the CPU. After the CPU had placed the address of the required memory location on to the address bus .it would indicate to the memory that it wished to read the value by activating the relevant line in the co
16、ntrol bus .The memory would respond by placing the contents of the memory location ad data on to the data bus ,and this would then be read by the CPU. Within the system bus, the address bus is an output bus from the CPU and an input bus to the other devices. The control bus consists of a number of l
17、ines, each of which may be either a control output from the CPU or a control input to the CPU. The data bus however acts as both an input bus and an output bus depending on whether the CPU is reading or writing data.Fig.4-4 shows that all devices in the system are connected together by the data bus
18、and this means that, potentially at least, the outputs of all the memory and I/O devices are connected. If this were in fact to happen it would cause the destruction of several or all of the connected devices, because some devices would be trying to drive the bus to a logic 1 state while others were
19、 trying to drive it to a logic 0 state2.To avoid this problem, the data bus connections of each device are capable of being placed into a third, high impedance state where the device no longer has any loading effect on the bus. This allows other devices connected to the data bus to output their data
20、 on to this bus when they are correctly enabled, which in turn means that only one device should be enabled at any one time to the data bus3.The ability of a device to be either at a logic I or at a logic 0 or in a high impedance condition in relation to the data bus is called a tristate condition,
21、and is an essential feature of devices which share a common data bus . In the example of Fig.4-4 the data bus has eight lines, and hence the range of values which a single item of data can take is restricted to that which can be represented by 8 binary digits or bits. Eight bits are referred to as a
22、 byte, and can represent a decimal number from 0 to 255；Likewise the address bus ,consisting of sixteen lines, can represent an address number in the range 0 to 65535.This number is usually abbreviated to the binary equivalent of the decimal number and expressed as 64K,where K is equal to 1024 in th
23、e binary number system. To the CPU, the system appears as a series of 64K consecutive memory locations, each capable of storing an 8 bit binary value. The CPU will contain a number of registers which are used to manipulate the data and its addresses. In the example chosen, these data registers will
24、be 8 bit registers and all data manipulations will be performed on 8 bit quantities. The CPU is therefore referred to as an 8 bit CPU, However, registers which support address manipulations need to be 16 bit registers because of the 16 bit address bus. The size of the address bus is independent of t
25、he size of the data bus ,so that 16 bit or 32 bit CPUs may typically have a 16 bit,24 bit or 32 bit address bus. It is normal when working with microprocessors to represent binary numbers as hexadecimal (base 16) values, because a single hexadecimal hex)digit corresponds to a group of four consecutive binary The hexadecimal number is easier to read and write than its binary equivalent, and it requires only simple mental calculation in
