1、Input/Output Accessing In this article, we will look at the three basic methods of I/O accessing programmed I/O, interrupt-driven I/O, and direct memory access (DMA). The key issue that distinguishes these three methods is how deeply the processor is involved in I/O operations. The discussion emphas
2、izes interrupt-driven I/O, because it is based on the concept of interrupt handling, which is a general problem that goes beyond Input/Output operations. The study of interrupt handling also aids in understanding the general concept of exception processing, which is an important issue not only for I
3、/O, but also for interfacing a computer with other system control functions. Addressing I/O Registers Input/Output devices communicate with a processor through Input/Output ports. Through the input ports, s processor receives data from the I/O devices. Through the output ports, a processor sends dat
4、a to the I/O devices. Each I/O port consists of a small set of registers, such as data buffer registers (the input buffer and/or the output buffer), the status register, and the control register. The processor must have some means to address these registers while communicating with them. There are t
5、wo common methods of addressing I/O register memory-mapped I/O and direct I/O. 1. Memory-Mapped I/O Memory-mapped I/O maps the I/O registers and main memory into a unified address space in the computer system. I/O registers share the same address space with main memory, but are mapped to a specific
6、section that is reserved just for I/O. Thus, the I/O register can be addressed in ordinary memory reference instructions as if they are part of the main memory locations. There are no specially designed I/O instructions in the instruction set of the system. Any instruction that references a location
7、 in this area is an I/O instruction. Any instruction that can specify a memory address is capable of performing I/O operations. The Motorola MC68000 is an example of a computer system that uses this addressing method. 2. Direct I/O The method of addressing I/O registers directly without sharing the
8、address space with the main memory is called direct I/O or I/O-mapped I/O. In other words, I/O registers are not mapped to the same address space with the main memory. Each I/O register has an independent address space. As a result, instructions that reference the main memory space cannot be used fo
9、r Input/Output. In the instruction set of the computer system, special I/O instructions must be designed for I/O operations. In these I/O instructions, distinct I.D. numbers must be used to address different I/O communication channels (i.e., I/O ports). They are called port numbers. The I/O register
10、s of an I/O port are connected to the system I/O bus, through which the processor can reference the I/O registers directly to send/receive data to/from an I/O device. An I/O port number is not from the same address space as main memory. The Pentium is an example of a computer system that uses the di
11、rect I/O addressing method. It has a 64 GB memory address space (32 address bits) and, at the same time, a 64 KB I/O address space (16 bits I/O address/port number). We can compare memory-mapped I/O and the direct I/O and the direct I/O as follows: Memory-mapped I/O uses ordinary memory reference in
12、structions to access I/O, so it provides flexibility for I/O programming and simplifies I/O software. Direct I/O does not provide any flexibility in I/O programming, since only a small set of special I/O instructions are allowed to reference I/O registers. for memory-mapped I/O, the processor uses t
13、he same address lines to access all the addressable I/O registers and the same data lines to send/receive data to/form these registers. This simplifies the connection between I/O port and the processor, and thus leads to a low-cost hardware design and implementation. For direct I/O, the connection b
14、etween I/O ports and the processor may be more expensive. This is because either (1) special hardware is needed to implement separate I/O address lines or (2) when memory address lines are used for I/O； a special flag is needed, indicating that the requested address is for an I/O operation. In spite
15、 of the advantage of using ordinary memory reference instructions to access I/O registers, memory-mapped I/O may complicate the control unit design in regards to the implementation of I/O-related instructions. This is because usually the I/O bus cycles need to be longer than the equivalent memory bu
16、s cycles, and this means that the design of different timing control logic is required. This can be used to explain why memory-mapped I/O benefits programmers, but not electronics engineers. Direct I/O addressing has another advantage over memory-mapped I/O in that low-level debugging on a different
17、iated addressing system may be easier, because break-points or error traps can be imposed more generally. with memory-mapped I/O, I/O registers share the same address space with main memory； hence, the memory space available for programs and data is reduced. For direct I/O addressing, I/O does not s
18、hare memory space with main memory, and a single contiguous memory space can be maintained and used by programmers. Programmed I/O Programmed I/O requires that all data transfer operations be put under the complete control of the processor when executing programs. It is sometimes called polling, bec
19、ause the program repeatedly polls (checks) the status flag of an I/O device, so that its input/output operation can be synchronized with the processor. A general flowchart of such a program is shown in Figure 1. The program continuously polls the status of an I/O device to find out whether (1) data
20、is available in the input buffer or (2) the output device is ready for receiving data from the processor. If the status shows “available” the program will execute a data transfer instruction to complete the I/O operation； otherwise, the busy status of the I/O device will force the program to circula
21、te in a busy-waiting loop until the status becomes available. Such a busy-waiting loop, which continuously checks the status of data availability (for input) or device availability (for out-put), forms the typical program structure of programmed I/O. It is this time-consuming busy-waiting loop that
22、wastes processor time and makes programmed I/O very inefficient. The processor must be involved continuously in the entire I/O process. During this time interval, the processor cannot perform any useful computation, but only serve a single I/O device. For certain slow I/O devices, this busy-waiting
23、loop interval may be long enough that the processor could execute millions of instructions before the I/O event occurs, e.g., a key stroke on a keyboard. The operational mode lf programmed I/O stated above is characterized by the busy waiting loop of the program, during which the processor spends ti
24、me polling an I/O device. Because of the dedication of the processor to a single task, this mode of programmed I/O is called dedicated polling or spin polling. Although dedicated polling is highly inefficient, sometimes it is necessary and even unavoidable. In a particular case, if an urgent event n
25、eeds an immediate response without delay, then dedicated polling by a dedicated processor may be the best way to handle it. Once the expected event happens, the processor can tract to it immediately. For example, certain real time systems (e.g., radar echo processing systems) require a reaction to i
26、ncoming data that is so quick that even an interrupt response is too slow. Under such a circumstance, only a fast dedicated polling loop may suffice. Another mode of operation of programmed I/O is called intermittent polling or timed polling. In this mode, the processor may poll the device at a regu
27、lar timed interval, which can be expected or prescheduled. Such a device can be found in many embedded systems where a special-purpose computer is used for process control, data acquisition, environmental monitoring, traffic counting, etc. these devices, which measure, collect, or record data, are u
28、sually polled periodically in a regular schedule determined by the needs of the application. Such a method of intermittent polling can help save time lost in spin polling and avoid the complexity of interrupt processing. However, it should be noted that intermittent polling may not be applicable in some special cases, in which there is only one device to be polled and the correct polling rate must be achieved with the
