1、1 AT89C2051 Microcontroller Instructions 1.1 Features Compatible with MCS-51 Products 2 Kbytes of Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles 2.7 V to 6 V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-Level Program Memory Lock 128 x 8-Bit Internal RAM 15 Programmable
2、 I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial UART Channel Direct LED Drive Outputs On-Chip Analog Comparator Low Power Idle and Power Down Modes 1.2 Description The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2 Kbytes of Flash programm
3、able and erasable read only memory (PEROM). The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a
4、powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C2051 provides the following standard features: 2 Kbytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architect
5、ure, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The 2 Idle Mode stops the CPU while allowing t
6、he RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. 1.3 Pin Configuration 1.4 Pin Description VCC Supply voltage. GND Ground. Port 1 P
7、ort 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers
8、can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during Flash pro
9、gramming and program verification. Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1
10、s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that 3 are externally being pulled low will source current (IIL) because of the pullups. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port)
11、 P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) Port 3 also serves the functions of various special features of the AT89C2051 as listed below: 1.5 Oscillator Characteristics XTAL1 and XTAL2 are the input and output,
12、 respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Fig
13、ure 2. There are no re-quirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divideby-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. 1.6 Special Function Registers A map of the on-
14、chip memory area called the Special Function Register (SFR) space is shown in the table below. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses. to these addresses will in general return random data, and write accesses will h
15、ave an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea tures. In that case, the reset or inactive values of the new bits will always be 0. 1.7 Restrictions on Certain Instructions The AT89C2051 and is an economical and cost-effective member of Atmels growing
