1、 附录 B 翻译原文 Electronic design automation Keyword EDA； IC；VHDL language； FPGA PROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then
2、, as the number of logic gates per chip passes the million marks, verification of a designs correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements witho
3、ut too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money. PARLEZ-VOUS SUPERLOG? A system on a chip comprises both circu
4、itry and the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chips functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is given to the pro- gram
5、mars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virology or VHDL, while the part that will end up as software is most often described in the programming language C or C+. The use
6、 of these disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion. It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification righ
7、t through to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existin
8、g language to meet system-on-chip needs. Among the candidates for extension were C, C+, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing m
9、ethodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then th
10、ey spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even
11、 functions like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directl
12、y. It is important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently Co-Design identified a number o
13、f electronic design automation companies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process. ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a modeling platform that extends the capabilities and
