1、毕业设计说明书（论文） 第 1 页共 4 页 AT89C51 PLAYBACK DEVICE The features of AT89C51 are: Compatible with MCS-51； 4K Bytes of In-System Reprogrammable Flash Memory； 1,000 Write/Erase Cycles； Fully Static Operation: 0 Hz to 24 MHz； Three-level Program Memory Lock； 128 x 8-bit Internal RAM； 32 Programmable I/O Line
2、s； Two 16-bit Timer/Counters； Six Interrupt Sources； Programmable Serial Channel；Low-power Idle and Power-down Modes。 Description： The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt archi
3、tecture, a full duple serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial p
4、ort and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description： VCC： Supply voltage. GND； Ground. Port 0： Port 0 is an 8-bit open-drain bi-directional I/O port
5、. As an output port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has internal
6、pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification7. Port 1： Port 1 is an 8-bit bi-directional I/O port with internal pull ups. The Port 1 output buffers can sink/sou
7、rce four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes duri
8、ng Flash programming and verification. Port 2： Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pin
9、s that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, it uses stron
10、g internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3
11、： Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will s
12、ource current (IIL) because of the pullups. Port 3 also serves 毕业设计说明书（论文） 第 2 页共 4 页 the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. RST： Reset input. A high on this pin for two machine cycle
13、s while the oscillator is running resets the device. ALE/PROG： Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rat
14、e of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only d
15、uring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode8. PSEN： Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external prog
16、ram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP： External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0
17、000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP. XT
18、AL1： Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2： Output from the inverting oscillator amplifier. Oscillator Characteristics： XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as
19、an on chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from 毕业设计说明书（论文） 第 3 页共 4 页 an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of
20、 the external clock signal, since the input to the internal clocking circuitry is through a divide-by two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. AT89C51 应用说明 AT89C51 的主要性能参数 ： 与 MCS-51 产品指令系统完全兼容 ； 4k 字节可重擦写FLASH 闪速存储器 ； 1000 次擦写周期 ； 全静态操作： 0Hz
21、24MHz； 三级加密程序存储器 ；1288 字节内部 RAM； 32 个可编程 I/O 口线 ； 2 个 16 位定时 /计数器 ； 6 个中断源 ； 可编程串行 URAR 通道 ； 低功耗空闲和掉电模式 。 功能特性概述 ： AT89C51 提供以下标准功能： 4k 字节 FLASH 闪速存储器， 128 字节内部 RAM， 32 个 I/O 口线， 2 个 16 位定时 /计数器，一个 5 向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时， AT89C51 降至 0Hz 的静态逻辑操作，并支持两种可选的节电工作模式。空闲方式体制 CPU 的工作，但允许 RAM，定时 /
22、计数器，串行通信口及中断系统继续工作。掉电方式保存 RAM 中的内容，但振荡器体制工作并禁止其他所有不见工作直到下一个硬件复位 。 管脚说明： VCC：供电电压。 GND：接地。 P0 口： P0 口为一个 8 位漏级开路双向 I/O 口，每脚可 吸收 8TTL 门电流。当 P1 口的管脚第一次写 1 时，被定义为高阻输入。 P0 能够用于外部程序数据存储器，它可以被定义为数据 /地址的第八位。在 FIASH 编程时， P0 口作为原码输入口，当 FIASH 进行校验时， P0 输出原码，此时 P0 外部必须被拉高。 P1 口： P1 口是一个内部提供上拉电阻的 8 位双向 I/O 口， P1
23、 口缓冲器能接收输出4TTL 门电流。 P1 口管脚写入 1 后，被内部上拉为高，可用作输入， P1 口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在 FLASH 编程和校验时， P1 口作为第八位地址接收。 P2 口： P2 口为一个内部上拉电阻的 8 位双向 I/O 口， P2 口缓冲器可接收，输出 4个 TTL 门电流，当 P2 口被写“ 1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时， P2 口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。 P2口当用于外部程序存储器或 16 位地址外部数据存储器进行存取时， P2 口输出地址的高八位。在给出地址“ 1”时，它利用内部上拉优势，当对外部八位地址数据存储器进行读写时， P2 口输出其特殊功能寄存器的内容。 P2 口在 FLASH 编程和校验时接收高八位地址信号和控制信号。 P3 口： P3 口管脚是 8 个 带内部上拉电阻的双向 I/O 口，可接收输出 4 个 TTL 门电流。当 P3 口写入“ 1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平， P3 口将输出电流（ ILL）这是由于上拉的缘故。 P3 口也可作为 AT89C51 的一些特殊功能口，如下表所示：
