1、附录 A ATmega8 The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle.The resulting archi
2、tecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features:8K bytes of In-System Programmable Flash with Read-While-Write capabilities,512 bytes of EEPROM,1K byte of SRAM,23general purpose I/O
3、lines,32 general purpose working registers, three flexibleTimer/Counters with compare modes, internal and external interrupts, a serial programmableUSART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eightchannels in TQFP and MLF packages) where four (six) channels have 10-bit accurac
4、yand two channels have 8-bit accuracy, a programmable Watchdog Timer with InternalOscillator, an SPI serial port, and five software selectable power saving modes. The Idlemode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interruptsystem to continue functioning. The Power-down
5、 mode saves the register contents butfreezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
6、Reduction mode stops the CPU and all I/O modules except asynchronous timer andADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consump
7、tion. The device is manufactured using Atmels high density non-volatile memory technology.The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program
8、can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmabl
9、e Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemb
10、lers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. The AVR provides several different interrupt sources. These interrupts and the separateReset Vector each have a separate Program Vector in the Program memory space. Allinterrupts are assigned individual enable bits which m
11、ust be written logic one togetherwith the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the Program Counter value, interrupts may be automatically disabledwhen Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves softwaresecurity. Whe
12、n an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled. The user software can write logic one to the I-bit to enable nested interrupts.All enabled interrupts can then interrupt the current interrupt routine. The I-bit isautomatically set when a Return from
13、 Interrupt instruction RETI is executed. There are basically two types of interrupts. The first type is triggered by an event thatsets the Interrupt Flag. For these interrupts, the Program Counter is vectored to theactual Interrupt Vector in order to execute the interrupt handling routine, and hardw
14、areclears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing alogic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembereduntil the interrupt i
15、s enabled, or the flag is cleared by software. Similarly, if one ormore interrupt conditions occur while the global interrupt enable bit is cleared, the correspondingInterrupt Flag(s) will be set and remembered until the global interrupt enablebit is set, and will then be executed by order of priori
16、ty. The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappearsbefore the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it w
17、ill always return to the main program and executeone more instruction before any pending interrupt is served.Note that the Status Register is not automatically stored when entering an interrupt routine,nor restored when returning from an interrupt routine. This must be handled bysoftware. When using
18、 the CLI instruction to disable interrupts, the interrupts will be immediatelydisabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneouslywith the CLI instruction. The following example shows how this can be used toavoid interrupts during the timed EEPROM write
19、 sequence. The interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum. After four clock cycles, the Program Vector address for the actual interrupthandling routine is executed. During this 4-clock cycle period, the Program Counter ispushed onto the Stack. The Vec
20、tor is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycleinstruction, this instruction is completed before the interrupt is served. If an interruptoccurs when the MCU is in sleep mode, the interrupt execution resp
21、onse time isincreased by four clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode.A return from an interrupt handling routine takes four clock cycles. During these fourclock cycles, the Program Counter (2 bytes) is popped back from the Stack, the StackPoint
22、er is incremented by 2, and the I-bit in SREG is set. The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memoryfor program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash isorganized as 4K x 16 bits. For software security, the Flash Program memory space isdiv
23、ided into two sections, Boot Program section and Application Program section. The lower 1120 Data memory locations address the Register File, the I/O Memory, andthe internal data SRAM. The first 96 locations address the Register File and I/O Memory,and the next 1024 locations address the internal da
24、ta SRAM.The five different addressing modes for the Data memory cover: Direct, Indirect withDisplacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. Inthe Register File, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches
25、 the entire data space.The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register.When using register indirect addressing modes with automatic pre-decrement and postincrement,the address registers X,Y and Z are decremented or incremented.The 3
26、2 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internaldata SRAM in the ATmega8 are all accessible through all these addressing modes. The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separatedata space, in which single bytes can be read and wr
27、itten. The EEPROM has anendurance of at least 100,000 write/erase cycles. The access between the EEPROMand the CPU is described bellow, specifying the EEPROM Address Registers, theEEPROM Data Register, and the EEPROM Control Register.“Memory Programming” on page 219 contains a detailed description o
28、n EEPROM Programmingin SPI- or Parallel Programming mode. All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations areaccessed by the IN and OUT instructions, transferring data between the 32 general purposeworking registers and the I/O space. I/O Registers within the address
29、range 0x00 -0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,the value of single bits can be checked by using the SBIS and SBIC instructions. Referto the instruction set section for more details. When using the I/O specific commands INand OUT, the I/O addresses
30、 0x00 - 0x3F must be used. When addressing I/O Registersas data space using LD and ST instructions, 0x20 must be added to these addresses. The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, andUSART. The I/O clock is also used by the External Interrupt module, but no
31、te that someexternal interrupts are detected by asynchronous logic, allowing such interrupts to bedetected even if the I/O clock is halted. Also note that address recognition in the TWImodule is carried out asynchronously when clkI/O is halted, enabling TWI address receptionin all sleep modes. XTAL1
32、 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartzcrystal or a ceramic resonator may be used. The CKOPT Fuse selects between two differentOscillator amplifier modes. When CKOPT is programmed, the Oscillator outputwill oscillate a full rail-to-rail swing on the output. This mode is
