1、附录 A Research of Parameter Adjustable Harmonic Signal GeneratorBased on DDS LI Wei College of Computer and InformationEngineeringHohaiUniversity Changzhou, 213022, China liwei_ ZHANG Jinbo College of Computer and InformationEngineering Hohai University Changzhou, 213022, C Abstract Harmonic signal g
2、enerator whose frequency, phase andharmonic proportion areadjustable is designed for thedetecting equipment of power system. The principle ofDDS and the design requirement are introduced. Then thealgorithm of ROM compression based on the symmetry ofsine wave is expounded. Finally, using Altera FPGA,
3、 thedetail design of the whole system is presented and testwaveforms are given. Test results indicate that the systemfulfils the design requirements. 1. Introduction An ideal power system supplies power with sine wave,but the practical waveform of power supply often hasmany harmonic components. The
4、basic reason ofharmonic is that the power system supplies power to theelectrical equipment with nonlinear characteristic. Thesenonlinear loads feed higher harmonic back to the powersupply, and make the waveform of current and voltage inpower system produce serious distortion.In the detection field o
5、f power system, standard signalgenerators which can simulate the power harmonic arehighly needed to calibrate the power detecting equipment,such as phase detector, PD detector, and so on. So theresearch of parameter adjustable harmonic signalgenerator provides the exact basis for the stable operatio
6、nof power detecting equipment, and has great economic benefit and social value. 2. Principle of direct digital synthesis Direct digital synthesis (DDS) is a new frequencysynthesis technology which directly synthesizeswaveform on the basis of phase. Using the relationshipbetween phase and amplitude,
7、the phase of waveform is segmented and assigned relevant addresses. In each clockperiod, these addresses are extracted and the relevantamplitudes are sampled. The envelope of these sampledamplitudes is the expected waveform. If the clockfrequency is constant, the frequency of output signal isadjusta
8、ble with different extracted steps of addresses. DDS is composed ofphase accumulator, ROM table, DAC and LPF. In eachclock period, the output of phase accumulator isaccumulated with frequency control word, and high L-bitof the output are used as address to query the ROM table.In the ROM, these addre
9、sses are converted to the sampledamplitudes of the expected waveform. Then DACconverts the sampled amplitudes to ladder wave. In theLPF, the ladder wave is smoothed, and the output is thecontinuous analog waveform. Suppose that the clock frequency is fc, frequencycontrol word is K, phase accumulator
10、 is N-bit, then outputfrequency is fout=(K/2N)fc, frequency resolution isfmin=fc/2N. According to the Nyquist Sample Criterion,output frequency upper limit is fmax0.5fc. Because of thenon-ideal characteristic of LPF, output frequency upperlimit of DDS is fmax=0.4fc. 3. Scheme design 3.1. Design requ
11、irements The goal of the system is to design a harmonic signalgenerator, whose frequency, phase and harmonicproportion are adjustable. The output waveform iscomposed of fundamental wave, 3th harmonic, 5thharmonic and 7th harmonic. Frequency resolution is 1Hz.The adjustable range of initial phase is
12、02 and itsresolution is 1o. The adjustable range of harmonicproportion is 050% and its resolution is 1%.According to the design requirements, system clockfrequency is 15MHz and phase accumulator is 24-bit. Inorder to make the most of EAB, 2118 bits ROM table isadopted. 11-bit phase control word is u
13、sed to meet therequirement of initial phase resolution. 7-bit proportioncontrol word is adopted to realize the setting of harmonicproportion. 3.2. Algorithm of ROM compression As is known, phase truncation error is the main factorof output waveform distortion. To avoid this, the ROMsize must be expo
14、nentially increased, however the EABof FPGA is limited. So the algorithm of ROMcompression based on the symmetry of sine wave isadopted in the system.Sine wave of one period is divided into 4 sections:0/2 、 /2 、 3/2 、 3/22. Using thesymmetry of sine wave, sampled amplitudes of the firstsection are s
15、tored in the ROM table. By addressconversion and amplitude conversion, sampledamplitudes of one period sine wave can be generated. Bythis means, the ROM size is a quarter of the previous size.In the same ROM, sampling points can be increased by 4times with this method. Sampled amplitudes of quarter
16、wave arestored in the ROM table. The output address of phaseaccumulator is (L+2)-bit. The low L-bit are used to querythe ROM table while the high 2-bit are used to identifyphase sections. When the highest bit is 1, the output ofROM table should be symmetrically converted by theamplitude convertor. W
17、hen the second highest bit is 1, theL-bit address should be symmetrically converted by theaddress convertor. 4. System design based on FPGA The system can be divided into two function modules:sine wave generation module and harmonic synthesismodule. Sine wave generation module is the key part ofthe
18、system. It can be divided into phase accumulatormodule and ROM compression module . Altera FPGAEP2C5Q208C8 is adopted as the core component of thesystem. VHDL is used to program the whole system.Compilation and simulation are implemented in Quartus . 4.1. Sine wave generation module phase accumulato
19、r moduleis composed of 24-bit accumulator and 11-bit adder.Under the control of system clock, the output of 24-bitaccumulator is accumulated with 9-bit frequency controlword. Then 11-bit adder adds 11-bit phase control word tothe output of accumulator. High 13-bit of the final resultare used as addr
20、ess to query the ROM compressionmodule.ROM compression module is composed of addressconvertor, amplitude convertor and ROM table. 13-bitaddress of phase accumulator module is divided into threeparts. The highest bit is used as trigger signal of theamplitude convertor. The second highest bit is used
21、astrigger signal of the address convertor. The low 11-bit areused to query the ROM table. Then sampled amplitudesof sine wave are generated. Simulation result of sine wave generation module isshown in Fig.4. Frequency control word is set as 50 whilephase control word is set as 180. When the enable s
22、ignalis turned into low level, the first output value is thewaveform data of address 180 in the ROM table. Witheach rising edge of system clock, the waveform data ofaddress 180, 181, 182, 183 are sent out. The output valuesare respectively 76, 76, 77, 77. 4.2. Harmonic synthesis module Harmonic synt
23、hesis module implements the synthesisof fundamental wave, 3th harmonic, 5th harmonic and 7thharmonic. The 3th, 5th and 7th harmonic data arerespectively multiplied by their proportion control words.Then the results of multiplication are added to thefundamental wave data. The realization of multiplic
24、ationis the emphasis of the module.Because it is difficult to implement the multiplicationof floating-point format on FPGA, harmonic proportion isdivided into numerator and denominator. The numeratoris defined as proportion control word while thedenominator is 100. Firstly, harmonic data is multipli
25、edby the proportion control word in the multiplier. Then, theproduct of multiplier is divided by 100 in the divider.Finally, the remainder is excluded and the quotient ispreserved. Using Altera IP tools, the multiplier and thedivider of harmonic synthesis module are realized. Blockdiagram of harmoni
26、c synthesis module is shown. Simulation result of harmonic synthesis module is. Control words are set before 2.0ms.Fundamental wave frequency is 50Hz, and its initialphase is 0o. The 3th harmonic frequency is 150Hz, initialphase is 45o and proportion is 50%. The 5th harmonicfrequency is 250Hz, initi
27、al phase is 90o and proportion is25%. The 7th harmonic frequency is 350Hz, initial phaseis 135o and proportion is 17%. When enable signal isturned into low level, harmonic synthesis module beginsto generate the harmonic synthesis data. 5. Test results Figure 7. Two-channel sine waves (frequency is 50Hz and phase difference is 180o)
