1、 毕业设计 说明书 英文文献及中文翻译 学生姓名： 学号： 学 院： 专 业： 指导教师： 2012 年 6 月 郭枫 0805074411 信息与通信工程学院 通信工程 李 沅 An alternative method of precise frequency by the aid of a DDS Contents A method of frequency measurement based on a closed loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (
2、DDS) is presented in this paper. The DDS serves as reference sinewave signal generator acting at one of the FCs inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the comparison of the two signals a logic output that controls an up/down counter is prod
3、uced. The counters output acting as the Frequency Setting Word (FSW) instructs the DDS to produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS
4、 and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associated stages up to the instruments display are presented. 1 Introduction The most commonly used frequency measurement technique adopts counters that count the pulses of the unknown frequ
5、ency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency are counted during one or more periods of the unknown one are also common. In the latter case, the period instead of the frequency is estimated .Some papers in 1 in the literature d
6、eal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (heart) signals (a few hertz) or in the mains frequency (50-60 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In 2
7、, the frequency is calculated by the method of look-up tables. Others 4-6 are microprocessor or microcontroller based. The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its close
8、d-loop form characterizes the proposed method in this paper. By the term closed-loop we denote some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency comparison stage which consecutively forces it to approximate the unkno
9、wn (input) frequency. The device that produces the above mentioned waveform of controlled frequency is a Direct Digital Synthesizer. 2 Direct Digital Synthesis A typical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine look-up table, LUT). These samples are swept i
10、n a controlled manner by the aid of a Frequency Setting Word (FSW), which determines the phase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in higher frequency resolution are also available. A phase accumulator produces the successive addresses of the sine look-up table and ge
11、nerates a digitized sine wave output. The digital part of the DDS, the phase accumulator and the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the
12、digitized sinewave, producing a continuous output signal. In the applications where a square wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use e.g. the MSB of the accumulators output instead of the filtered and hard limited waveform because signi
13、ficant jitter will be encountered. The frequency of the output signal for an n-bit system is calculated in the following way； If the phase step is equal to one, the accumulator will count by ones, taking 2n clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This
14、 is the lowest frequency that the system can generate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator counting by twos, taking 12n clock cycles to complete one cycle of the output sinewave. It can easily be shown that for any integer m, where m 12n , the number of
