1、 外文文献翻译（译成中文 1000 字左右）： 【主要阅读文献不少于 5 篇，译文后附注文献信息，包括：作者、书名（或论文题目）、出版社（或刊物名称）、出版时间（或刊号）、页码。提供所译外文资料附件（印刷类含封面、封底、目录、翻译部分的复印件等网站类的请附网址及原文）】 外文文献： 1. Description The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory(PEROM).
2、 The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By
3、 combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. 2.Features Compatible with MCS-51 TM Products 8K Bytes of In-System Reprogrammable Flash
4、 Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHZ Three-Level Program Memory Lock 256 x 8-Bit Internal RAM 32 Programmable I/O Lines .Three 16-bit Timer/Counters Eight interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes The AT89C52 provi
5、des the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters， a six-vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation
6、down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but feezes the oscillator, disabling all other chip
7、functions until the next hardware reset. 3. Pin Description vcc Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidrectional I/O port. As an output port, each pin can sink eight TTL mputs. When ls are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 can
8、also be configured to be the multiplexed low order address/data bus during accesses to extemal program and data memory. In this mode, P0 has intemal pullups. Port 0 also receives the code bytes during Flash programming and outputs the de bytes during program verification. Extemal pullups are require
9、d during Program verification. Port 1 Port 1 is an 8-bit bidirectional 1/0 port with intemal pullups. The Port 1 output buffers can sink/source four TTL inputs. When Is are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are
10、 extemally being pulled low will source current (IlL) because of the intemal pullups. 1n addition, P1.0 and P1.1 can be configured to be the timer/counter 2 extemal count input(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively， as shown in the following table. Port 1 also rece
11、ives the low-order address bytes during Flash programing and verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When Is are written to Port 2 pins, they are pulled high by the internal pullups and can be us
12、ed as inputs. As inputs, Port 2 pins that are extemal1y being puIled low will source current (IIL) because ofthe intemal pullups. Port 2 emits the high-order address byte during fetches from extemal program memory and during accesses to extemal data memory that use 16-bit addresses (MOVX DPTR). 1n t
13、his application, Port 2 uses strong intemal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI)， Port 2 emits the contents of the P2 Special Function Register. Port 2 a1s0 receives the high-order address bits and some control signals during Flash pro
14、gramming and verification. Port 3 Port 3 is an 8-bit bidirectional 1/0 port with internal pullups.be Port 3 output buffers can sink/source four TTL inputs. When Is are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are exte
15、mal1y being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various specia1 features of the AT89C51, as shown in the following tab1e. Port 3 also receives some contro1 signa1s for F1ash programming and verification. RST Reset input. A high on this pin
16、 for two machine cycles while the osci1lator is running resets the device. ALEIPROG Address Latch Enab1e is an output pu1se for 1atching the 10w byte of the address during accesses to externa1 memory. This pin is a1so the program pu1se input (PROG) during F1ash programming. In norma1 operation, ALE
17、is emitted at a constant rate of 1/6 the oscillator frequency and may be used are externa1 timing or clocking purposes. Note, however, that one ALE Port Pin A1ternate Functions P 1.0 T2 (externa1 count input to Timer/Counter 2),clock-out P1.1 T2EX (Timer/Counter 2 capture/re1oad trigger and directio
18、n control) Port Pin A1ternate Functions P3.0 RXD (seria1 input port) P3 .1TXD (seria1 output port) P3.2 INT0 (extema1 interrupt 0) P3.3 INT1 (externa1 interrupt 1) P3.4 TO (timer 0 externa1 input) P3.5 T1 (timer 1 externa1 input) P3.6 WR (extema1 data memory write strobe) P3.7 RD (externa1 data memo
19、ry read strobe) Pu1se is skipped during each access to extERna1 data memory. If desired, ALE operation can be disab1ed by setting bit 0 of SFR 10cation 8EH. With the bit set, ALE is active on1y during a MOVX or MOVC instruction. Otherwise, the pin is weak1y pulled high. Setting the ALE-disab1e bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enab1e is the read strobe to externa1 program memory. When the AT89C52 is executing code from externa1 program memory, PSEN is
