1、附录 A 英文原文 1 The SerialPort Interface of the LCD Driver IC This section will describe how to control the register value of the LCD driver IC on the LTM. The LCD and touch panel module on the LTM is equipped with a LCD driver IC to support three display resolution and with functions of source driver,
2、serial port interface, timing controller, and power supply circuits. To control these functions, users can use FPGA to configure the registers in the LCD driver IC via serial port interface. Also, there is an analog to digital converter (ADC) on the LTM to convert the analog X/Y coordinates of the t
3、ouch point to digital data and output to FPGA through the serial port interface of the ADC.Both LCD driver IC and ADC serial port interfaces are connected to the FPGA via the 40-pin expansion header and IDE cable. Because of the limited number of I/O on the expansion header, the serial interfaces of
4、 the LCD driver IC and ADC need to share the same clock (ADC_DCLK) and chip enable (SCEN)signal I/O on the expansion header. To avoid both the serial port interfaces may interfere with each other when sharing the same clock and chip enable signals, the chip enable signal (CS), which is inputted into
5、 the ADC will come up with a logicinverter as shown in Figure1.1. Figure 1.1 The serial interface of the LCD touch panel module and AD7843 Users need to pay attention controlling the shared signals when designing the serial portinterface controller. The detailed register maps of the LCD driver IC ar
6、e listed in appendix chapter.The specifications of the serial port interface of the LCD driver IC are described below. The LCD driver IC supports a clock synchronous serial interface as the interface to a FPGA toenable instruction setting. Please notice that in addition to the serial port interface
7、signals, NCLKinput should also be provided while setting the registers. Figure 1.2 and Table1.1 show the frameformat and timing diagram of the serial port interface. The LCD driver IC recognizes the start of datatransfer on the falling edge of SCEN input and starts data transfer. When setting instru
8、ction, theTPG110 inputs the setting values via SDA on the rising edge of input SCL. Table 1.1 The timing parameters of the serial port interface The first 6 bits (A5 A0) specify the address of the register. The next bit means Read/Writecommand. “0” is write command. “1” is read command. Then, the ne
9、xt cycle is turn-round cycle.Finally, the last 8 bits are for Data setting (D7 D0). The address and data are transferred from theMSB to LSB sequentially. The data is written to the register of assigned address when “End oftransfer” is detected after the 16th SCL rising cycles. Data is not accepted i
10、f there are less or morethan 16 cycles for one transaction. Item Symbol Condition Min Max Unit SDA Setup Time ts0 SCEN to SCL 150 ns ts1 SDA to SCL 150 ns SDA Hold Time th0 SCEN to SCL 150 ns th1 SDA to SCL 150 ns Pulse Width tw1l SCL pulse width 160 ns tw1h SCL pulse width 160 ns tw2 SCEN pulse idt
11、h 1.0 ns Clock duty 40 60 % Figure 1.2 The frame format and timing diagram of the serial port interface 2Input timing of the LCD panel display function This section will describe the timing specification of the LCD synchronous signals and RGB data. To determine the sequencing and the timing of the i
12、mage signals displayed on the LCD panel, the corresponding synchronous signals from FPGA to the LCD panel should follow the timing specification. Figure 2.1LCD horizontal timing specification Figure 2.1 illustrates the basic timing requirements for each row (horizontal) that is displayed on the LCD panel. An active-low pulse of specific duration (time thpw in
