1、附录 3 英文资料 Power Management Techniques and Calculation Relevant Devices This application note applies to the following devices: C8051F000, C8051F001, C8051F002, C8051F005, C8051F006, C8051F010, C8051F011, C8051F012, C8051F012, C8051F015, C8051F016, and C8051F017. Introduction This application note di
2、scusses power management techniques and methods of calculating power in a Cygnet C8051F00x and C8051F01x Sock. Many applications will have strict power requirements, and there are several methods of lowering the rate of power consumption without sacrificing performance. Calculating the predicted pow
3、er use is important to characterize the systems power supply requirements. Key Points Supply voltage and system clock frequency strongly affect power consumption. Cygnets Socks feature power management modes: IDLE and STOP. Power use can be calculated as a function of system clock frequency, supply
4、voltage, and enabled peripherals. Power Saving Methods CMOS digital logic device power consumption is affected by supply voltage and system clock (SYSCLK) frequency. These parameters can be adjusted to realize power savings, and are readily controlled by the designer. This section discusses these pa
5、rameters and how they affect power usage. Reducing System Clock Frequency In CMOS digital logic devices, power consumption is directly proportional to system clock (SYSCLK) frequency: power=CV2, where C is CMOS load capacitance, V is supply voltage, and is SYSCLK frequency. Equation 1.CMOS Power Equ
6、ation The system clock on the C8051Fxxx family of devices can be derived from an internal oscillator or an external source. External sources may be a CMOS clock, RC circuit, capacitor, or crystal oscillator. For information on configuring oscillators, see application note: “AN02 - Configuring the In
7、ternal and External Oscillators.” The internal oscillator can provide four SYSCLK frequencies: 2, 4, 8, and16 MHz. Many different frequencies can be achieved using the external oscillator. To conserve power, a designer must decide what the fastest needed SYSCLK frequency and required accuracy is for
8、 a given application. A design may require a constant SYSCLK frequency during all device operations. In this case, the designer will choose the lowest possible frequency required, and use the oscillator configuration that consumes the least power. Typical applications include serial communications,
9、and periodic sampling with an ADC that must be performed. Some operations may require high speed operation, but only in short, intermittent intervals. This is sometimes referred to as “burst” operation. In the C8051Fxxx, the SYSCLK frequency can be changed at anytime. Thus, the device can operate at
10、 low frequency until a condition occurs that requires high frequency operation. Two examples of alternating between SYSCLK sources are (1) an internal oscillator/external crystal configuration, and (2) an external crystal/RC oscillator configuration. If the device is used for occasional high speed d
11、ata conversion, and a real-time clock is used for time-stamping the data, a combination internal oscillator and external crystal would be ideal. During sampling operations, the high speed internal oscillator would be used. When sampling is complete, the device could then use an external 32 kHz cryst
12、al to maintain the real-time clock. Once high speed operations are required again, the device switches to the internal oscillator as necessary (see Figure 1below). An example of this procedure is illustrated in application note “AN008 Implementing a Real-Time Clock”. The crystal oscillator and inter
13、nal oscillator may be operated simultaneously and each selected as the SYSCLK source in software as desired. To reduce supply current, the crystal may also be shutdown when using the internal oscillator. In this case, when switching from the internal to external oscillator the designer must consider
14、 the start-up delay when switching the SYSCLK source. The C8051F0xx devices have a flag that is set when the external clock signal is valid (XTLVLD bit in the OSCXCN register) to indicate the oscillator is running and stable. This flag is polled before switching to the external oscillator. Note that
15、 other operations can continue using the internal oscillator during the crystal start-up time. Some applications require intermittent high speed and accuracy (e.g., ADC sampling and data processing), but have lower frequency and accuracy requirements at other times (e.g., waiting for sampling interv
16、al), a combination of an external oscillator and RC circuit can be useful. In this case, the external RC oscillator is used to derive the lower frequency SYSCLK source, and the crystal is used for high frequency operations. The RC circuit requires a connection to VDD (voltage source) to operate. Bec
17、ause this connection could load the crystal oscillator circuit while the crystal is in operation, we connect the RC circuit to a general purpose port pin (see Figure 2 below). When the RC circuit is in use, the port pin connection is driven high (to VDD) by selecting its output mode to “push-pull” a
18、nd writing a 1 to the port latch. When the crystal oscillator is being used, the port pin is placed in a hi- Z condition by configuring the output mode of the port to “open-drain” and writing a 1 to the port latch. Note the RC circuit may take advantage of the existing capacitors used for the crysta
19、l oscillator. The start-up of the RC-circuit oscillator is nearly instantaneous. However, there is a notable start-up time for the crystal. Therefore, switching from the RC oscillator to the external crystal oscillator using the following procedure: 1. Switch to the internal oscillator. 2. Configure
20、 the port pin used for the RC circuit voltage supply as open-drain and write a 1 to the port pin (Hi-Z condition). 3. Start the crystal (Set the XFCN bits). 4. Wait for 1 ms. 5. Poll for the External Crystal Valid Bit (XTLVLD - 1). 6. Switch to the external oscillator. Switch from the external crystal oscillator to the RC oscillator as follows: 1. Switch to the internal oscillator. 2. Shutdown the crystal (clear the XFCN bits). 3. Drive the voltage supply port pin high (to VDD) by putting the port pin in
