1、An alternative method of precise frequency by the aid of a DDS Contents A method of frequency measurement based on a closed loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DDS) is presented in this paper. The DDS serves as reference sinewave signal generator act
2、ing at one of the FCs inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the comparison of the two signals a logic output that controls an up/down counter is produced. The counters output acting as the Frequency Setting Word (FSW) instructs the DDS to
3、produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter.
4、All the additional associated stages up to the instruments display are presented. 1 Introduction The most commonly used frequency measurement technique adopts counters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the pul
5、ses of a reference frequency are counted during one or more periods of the unknown one are also common. In the latter case, the period instead of the frequency is estimated .Some papers in 1 in the literature deal with the problem of low frequency measurement and are focusing in the frequency range
6、of cardiac (heart) signals (a few hertz) or in the mains frequency (50-60 Hz). These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In 2, the frequency is calculated by the method of look-up tables. Others 4-6 are microprocess
7、or or microcontroller based. The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closed-loop form characterizes the proposed method in this paper. By the term closed-loop we de
8、note some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency comparison stage which consecutively forces it to approximate the unknown (input) frequency. The device that produces the above mentioned waveform of controlled
9、frequency is a Direct Digital Synthesizer. 2 Direct Digital Synthesis A typical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine look-up table, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which determines the p
10、hase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in higher frequency resolution are also available. A phase accumulator produces the successive addresses of the sine look-up table and generates a digitized sine wave output. The digital part of the DDS, the phase accumulator a
11、nd the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitized sinewave, producing a continuous output signal. In the applications where a squa
12、re wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use e.g. the MSB of the accumulators output instead of the filtered and hard limited waveform because significant jitter will be encountered. The frequency of the output signal for an n-bit system
13、is calculated in the following way； If n the phase step is equal to one, the accumulator will count by ones, taking 2 clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolutio
14、n. Setting the FSW equal to two, results in the accumulator counting by twos, taking 2n?1 clock cycles to complete one n?1 cycle of the output sinewave. It can easily be shown that for any integer m, where m 2 , the number of clock cycles taken to generate one cycle of the output sine wave is 2n /m,
15、 and the output frequency (fDDS) and the frequency resolution (fres) are given by the following formulas： m fclk 2n n fres= fclk/ 2 fDDS= For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is 7.68 mHz. If n is increased to 48, with the same clock frequency, a resoluti
16、on of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a
17、closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that
18、 uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolut
19、ion will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n ) becomes finer i.e. it improves. The impact of the clock frequency decrease is the subsequent d
20、ecrease of its maximum output frequency that limits the counters maximum count. The major blocks have been shown . Among them are the Frequency Comparator and the DDS. To overcome some disadvantages of the specific frequency comparator a correction stage has been incorporated. This stage is also use
21、d for the measurement extraction in order to display the correct reading. 3.1 Operation of the circuit The circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half
22、 of its maximum. In addition, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on the output of the Frequency Comparator. The approximation pr
23、ocedure stops when the step size decreases to one. After that, an up/down counter substitutes the approximation mechanism. The digital FSW, after the appropriate correction and decoding, is presented in an output device i.e. an LCD display or any other suitable means. Alternatively, it can be digita
24、lly recorded or it can be read by a computer. As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled Synthesizer which is forced to produce a frequency almost equal to the unknown one. 3.2 Frequency comparison The frequency comparator seems to b
25、e the most critical stage of the design. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flip-flop. The function of the frequency comparator is based on the
26、 principle that the lower frequency, i.e. larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, th
27、e circuit operates as follows: When the first counter (#1) encounters two rising edges of the unknown frequency in one period of the DDS, it sets the output of the RS flip-flop. The logic 1 of the RS flip-flop acting at the U/D control input of the Up/Down counter forces the DDS to rise its output f
28、requency. On the contrary, when the second counter (#2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flip-flops output. This action decreases the frequency of the DDS. At a first glance one could think that the synthesized frequency could reach
29、the measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as hysteresis. Hysteresis depends on the initial timing r
30、elation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The ambiguity settles when two rising edges of the higher frequency waveform occur during one period of the lower one.
31、 If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the comparators output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage com
32、parator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situat
33、ion is controlled, as will be explained later. Although an analog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog compone
34、nts, wide frequency range of operation and shorter response time. 3.3 Interaction between frequency comparator and digital synthesizer After the successive approximation of the unknown frequency the Frequency Comparator realizes that the synthesized frequency is higher (lower) than the unknown one a
35、nd produces a logic 0 (1) at the output which commands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be realized by the frequency comparator and the synthesized frequency will keep on increasing for some clock cycles, until the comparator detects the correct relation of its two input frequencies, the unknown one and the DDS output.
