1、Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller Abstract With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discu
2、ss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from
3、 NASA Institute of Advanced Microelectronics (IAE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices. Index Terms Single Event Effects, Hardened-By-Design, microcontroller, radiation effects. I. INTRODUCTION NASA c
4、onstantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources 1,2. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercial state-
5、ofthe-art technologies, NASAs performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices u
6、sing design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, cost-effective, and reliable manner. However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qu
7、alification tests performed； what types of tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and S
8、EE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices? As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the des
9、ign library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months lat
10、er a NASA flight project enters the mix by designing a new device using Vendor As library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked. How complete was the test chip? Was there sufficient statistical coverage of all library elemen
11、ts to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example)
12、may be waived. Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) inc
13、lude the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies. The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the charact
14、eristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASAs Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations. III. HBD TECHNOLOGY EVALUATION USING
15、 THE 8051 MICROCONTROLLER With their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle
16、that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAE (the focus of this study). As these HBD technologies become available, validation of the technology, in
17、 the natural space radiation environment, for NASAs use in spaceflight systems is required. The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this contr
18、oller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are min
19、imized. The IAE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation hardened 8051, that built t
20、heir 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation. The objective of this work is the technology evaluation of the CULPRiT process 3 from IAE. The process ha
21、s been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done. In the performan
22、ce of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exerci
23、sed the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future. IV. TEST DEVICES Three devi
24、ces were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively. The Intel devices are the ROMless, CMOS version of the
25、classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intels P629.0 CHMOS III-E process. The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcont
26、rollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peri
27、pheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device oper
28、ation, were utilized in order to maximize the similarity between the Dallas and Intel test codes. The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to oper
29、ate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages； the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to
30、 be instruction set compatible with the MSC-51 family. V. TEST HARDWARE The 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other components of the DUT computer were removed from the immediate area of the irradiation beam. A small card (one
31、 per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This DUT Board was connected to the Main Board by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in
