1、PDF外文：http:/ Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller Abstract With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper,
2、we will discuss the implications of validating these methods for the single event effects （ SEE） in the space environment. Topics include the types of tests that are required and the design coverage （ i.e., design libraries: do they need validating for each application?） . Finally, an 8051 mic
3、rocontroller core from NASA Institute of Advanced Microelectronics （ IAE） CMOS Ultra Low Power Radiation Tolerant （ Culprit） design is evaluated for SEE mitigative techniques against two commercial 8051 devices. Index Terms Single Event Effects, Hardened-By-Design, microcontr
4、oller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources 1,2. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or m
5、ore generations of performance behind commercial state-of-the-art technologies, NASAs performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called har
6、dened-by-design （ HBD） .Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, cost-effective, and reliable manner. However, one question still exists: tr
7、aditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed； what types of tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and org
8、anizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID （ Co-60） and SEE （ heavy ion and/or proton） are required for device validation. So what is unique to HBD devices? As opposed to a regular commercial-off-the-shelf （ COTS） device or application specific integrat
9、ed circuit （ ASIC） where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we qualify a future device using the same library? Consider if Vendor A has designed a ne
10、w HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor As library. Does this device require complete radiation qualification testing? To answer this, other ques
11、tions must be asked. How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if pa
12、rt of the HBD was relying on inherent radiation hardness of a process, some of the tests （ like SEL in the earlier example） may be waived. Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power
13、supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations （ i.e., nonstatic operation） include the propagated effects of Single Event Transients （ SETs） . These can be a greater concern at higher frequencies. The point of the conside
14、rations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary.
15、 A task within NASAs Electronic Parts and Packaging （ NEPP） Program was performed to explore these types of considerations. III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLER With their increasing capabilities and lower power consumption, microcontrollers are increasingly bei
16、ng used in NASA and DOD system designs. There are existing NASA and DOD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontrol
17、ler being developed by Mission Research Corporation （ MRC） and the IAE （ the focus of this study） . As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASAs use in spaceflight systems is required. The 8051 microcontr
18、oller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAE chose this device to
19、 demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAE technology uses ultra low power, and layout and architecture HBD design rules to achieve their
20、results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center （ UTMC） , the commercial vendor of a radiation hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one devic
21、e structure makes the 8051an ideal vehicle for performing this technology evaluation. The objective of this work is the technology evaluation of the Culprit process 3 from IAE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done. In the performance of the technology evaluation, this task developed hardware and
