1、附录 A 科技文章摘译 MICROPROCESSOR REPORT Atmel AVR Brings RISC to 8-Bit World Better Performance Than Other 8-Bit Chips With Same Low Cost By Jim Turley Proving the adage that all technologies eventually filter down into commodity products, Atmel has brought RISC design philosophy to 8-bit micro-controller
2、s. Dubbed AVR, this new architecture provides all the usual benefits of RISC: faster clock rates, better performance, and more efficient compiler optimization. Atmel also promises better code density and lower cost than comparable 8-bit micro-controllers. AVR competes with several well-established m
3、icro-controller dynasties such as the 6805, 68HC11, and 8051.Competition also comes from Microchips PIC family, a more modern design thats expanded rapidly in the past few years. Atmel hopes AVR will appeal to embedded designers who are willing to tackle a new architecture to get more performance th
4、an the entrenched micro-controller families can provide. AVR is the first in-house CPU design from Atmel, a billion-dollar company better known for its flash memory and E2PROM products. The company also sells a dozen flash-based derivatives of the popular 8051family, which it produces under license
5、from Intel. Design Melds RISC and Micro-controller Ideas The CPU resembles most RISC processors but has smaller registers. It was originally developed by a pair of researchers in Trondheim,Norway, before their consultancy was acquired by Atmel in 1995. Core CPU development still takes place in Norwa
6、y, while memory and peripheral development is centered in Atmels San Jose (Calif.) facility. The core features 32 identical 8-bit registers, as Figure 1 shows. Any register can hold addresses or data. Since 8-bit address pointers are fairly worthless even in an 8-bit device, the last six registers c
7、an be used in pairs, as address pointers. Dubbed X, Y, and Z, these three meta-registers can be used for any load or store operation. The pointers can be post incremented or predecremented at the programmers option. Finally, a 6-bit displacement can be added to the contents of the pointer, a useful
8、option for addressing array elements. This mode is not available for the X pointer； that op code is reserved for the LDI (load immediate constant) instruction. Figure 1. Unlike other 8-bit controllers, AVR has a set of 32 8-bit registers. The last six registers can be paired to form three address po
9、inters. As with many low-end micro-controllers, the register file is mapped into the address space, and vice versa. The first 32 bytes of memory, 0x000x1F, correspond to registers R0R31. The chips status registerwhich contains the overflow, carry, sign, and other flagsas well as other internal regis
10、ters are also memory mapped. This allows any register to be manipulated using standard memory references instead of special control-register instructions. For all intents and purposes, the CPU has no pipeline. It retrieves both source operands, executes the instruction, and stores the result in a si
11、ngle clock cycle. Branch latency is one clock for taken branches. All operations are register-to-register； the chip follows a strict load/store model. The great majority of AVR instructions are 16 bits long. Only four 32-bit instructions exist, allowing limited use of absolute 16-bit addressing. AVR
12、 separates the program and data spaces； although data pointers can be 16 bits, the PC (program counter) is only 12 bits wide, for 8K of code space. Instruction Set As Regular As Possible The compact instruction set necessarily forces some compromises, the first of which affects immediate values (lit
13、erals). Very few instructions accept immediate values, and those that do (ADIW, SUBI, ORI, etc.) work only on the upper half (R16R31) of the register set, as Table 1 shows. Even after shaving a bit from the operand-specified field, these instructions sometimes have room for only 6-bit immediate valu
14、es. Table 1. Atmels AVR 8-bit RISC instruction set follows a strict load/store model, with a few simple indirect addressing modes, including post increment and preferment. The architecture also includes a number of individual bit-manipulation instructions. The ADIW and SBIW instructions (add/subtract immediate from word) are even more restrictive, operating on only the last eight registers, R24R31. These instructions are meant primarily to add small offsets (063 bytes) to the X, Y, and Z pointers.
